计算机组织与糸统结构 MIPS指令系统体系结构 MIPS Instruction set architecture (第五讲) 程旭 2000.3.20 北京大学计算机科学技术系 计算机系统结枃教硏室
GÜWÑÇj°_+ ÑÇj+´DÔ NJQTù;ùé NJQT!Jotusvdujpo!Tfu!Bsdijufduvsf ¯æ §ù;é ÄËZ Å 3111/4/31 È
本讲概况 上讲复习 ■MIPS指令系统体系结构 MIP的其他情况 ■ MIPS( PowerPC、VAX.80X86) 北京大学计算机科学技术系 计算机系统结枃教硏室
GÜWÑÇj°_+ ÑÇj+´DÔ þZZ ßZô NJQTù;ùé NJQT|ÚÇ=Z NJQT!)QpxfsQDWBY91y97*!
指令系统设计 软件 指令系统 / 硬件 北京大学计算机科学技术系 计算机系统结枃教硏室
GÜWÑÇj°_+ ÑÇj+´DÔ 7+îÑ Û¸Ï³ CÊ @Ê
执行周期 Instruction 从程序存储系统中获得指令 Fetch Instruction 确定所需的动作和指令大小 Decode Operand 定位并获得操作数数据 Fetch Execute 计算结果数值或状态 Result 在存储系统中存放结果,以备后用 Store Next 确定后续指令 Instruction 北京大学计算机科学技术系 计算机系统结枃教硏室
GÜWÑÇj°_+ ÑÇj+´DÔ |O ,QVWUXFWLRQ )HWFK ,QVWUXFWLRQ 'HFRGH 2SHUDQG )HWFK ([HFXWH 5HVXOW 6WRUH 1H[W ,QVWUXFWLRQ ¢ßc,|ϳkÛ¸ BnÔX|0`Û¸ûã n!Jk¡0DDB uk§pDêÕ ü,|ϳ,§pȹÛâü BnâÁÛ¸
上讲总结:|SA ·使用通用寄存器的oad- store结构; 支持如下寻址方式: displacement with an address offset size of12to 16bits、 immediate(size8to16bits),以及 register deferred; ·支持如下简单指令(因为它们决定执行的指令总数):load、 store、add、 subtract、 move register-register、and、 shift、 compare equal、 compare not equal branch with a Pc-relative address at least 8-bits long)、jump、cll以及 return; ·支持如下数据大小和类型:8位、16位、32位整数;以及 32位和64位EEE754浮点数 如果看重性能,就使用固定指令编码方案 如果看重代码大小,就使用可变指令编码方案 提供至少16个通用寄存器,以及单独的浮点寄存器; 确信所有的寻址方式都可以用于所有的数据传输指令; ·瞄准最低限要求的指令系统 北京大学计算机科学技术系 计算机系统结枃教硏室
GÜWÑÇj°_+ ÑÇj+´DÔ Süîü,<XORDGVWRUH§X× ÕVßÏãÖGLVSODFHPHQW ZLWKDQDGGUHVVRIIVHWVL]HRIWR ELWV à LPPHGLDWH VL]HWRELWV ¹ UHJLVWHUGHIHUUHG ÕVßT)۸ĴWÀn; XÛ¸DÅÖORDGÃVWRUHÃDGGà VXEWUDFWÃPRYHUHJLVWHUUHJLVWHUÃDQGÃVKLIWÃFRPSDUHHTXDOà FRPSDUHQRWHTXDOà EUDQFK ZLWKD3&UHODWLYHDGGUHVVDWOHDVWELWV ORQJ à MXPSà FDOO¹UHWXUQ ÕVßDBûã`O_Ö!Ã!Ã!HD× ¹ !` ! ,(((BD Vpß¡ûÑÈSü ÎnÛ¸êÕ Vpß¡·ÕûãÈSü ì۸êÕ ¤oÇåþîü,<ȹ)ÀXB,< BµÝXÏãÑùübÝXDBôgÛ¸ XÔ"$UX۸ϳ :âk ,6$
Instructions Words of the Machine's language More primitive than higher level languages e.g., no sophisticated control flow ° Very restrictive e.g., MIPS Arithmetic Instructions We will be working with the mips instruction set architecture similar to other architectures developed since the 1980s used by NEc, Nintendo, Silicon Graphics, Sony Design goals: maximize performance and minimize cost, reduce design time 北京大学计算机科学技术系 计算机系统结枃教硏室
GÜWÑÇj°_+ ÑÇj+´DÔ ,QVWUXFWLRQV e:RUGVRIWKH0DFKLQH¶V/DQJXDJH e0RUHSULPLWLYHWKDQKLJKHUOHYHOODQJXDJHV HJQRVRSKLVWLFDWHGFRQWUROIORZ e9HU\UHVWULFWLYH HJ0,36$ULWKPHWLF,QVWUXFWLRQV e:HZLOOEHZRUNLQJZLWKWKH0,36LQVWUXFWLRQVHWDUFKLWHFWXUH VLPLODUWRRWKHUDUFKLWHFWXUHVGHYHORSHGVLQFHWKH V XVHGE\1(&1LQWHQGR6LOLFRQ*UDSKLFV6RQ\ 'HVLJQJRDOV PD[LPL]HSHUIRUPDQFHDQGPLQLPL]HFRVW UHGXFHGHVLJQWLPH
MIPS arithmetic All instructions have 3 operands Operand order is fixed ( destination first Example: c code A =B+C MIPS code: add Ss0, Ssl, $s2 associated with variables by compiler) 北京大学计算机科学技术系 计算机系统结枃教硏室
GÜWÑÇj°_+ ÑÇj+´DÔ 0,36DULWKPHWLF e$OOLQVWUXFWLRQVKDYHRSHUDQGV e2SHUDQGRUGHULVIL[HG GHVWLQDWLRQILUVW ([DPSOH &FRGH $ %& 0,36FRGH DGGV VV DVVRFLDWHGZLWKYDULDEOHVE\FRPSLOHU
MIPS arithmetic Design Principle: simplicity favors regularity. Why? of course this complicates some things c code: A=b+C+d: EE F-A MIPS code: add sto, ss1, ss2 add sso, sto, $s3 sub ss4, Ss5, Ss0 Operands must be registers, only 32 registers provided Design Principle: smaller is faster. Why? 北京大学计算机科学技术系 计算机系统结枃教硏室
GÜWÑÇj°_+ ÑÇj+´DÔ 0,36DULWKPHWLF e'HVLJQ3ULQFLSOH VLPSOLFLW\IDYRUVUHJXODULW\ :K\" e2IFRXUVHWKLVFRPSOLFDWHVVRPHWKLQJV &FRGH $ %&' ( ) $ 0,36FRGH DGGW VV DGGV WV VXEV VV e2SHUDQGVPXVWEHUHJLVWHUVRQO\UHJLVWHUVSURYLGHG e'HVLJQ3ULQFLSOH VPDOOHULVIDVWHU :K\"
Registers vs Memory Arithmetic instructions operands must be registers, only 32 registers provided Compiler associates variables with registers What about programs with lots of variables Control Input Memory Datapath Output Processor vO 北京大学计算机科学技术系 计算机系统结枃教硏室
GÜWÑÇj°_+ ÑÇj+´DÔ 5HJLVWHUVYV0HPRU\ 3URFHVVRU ,2 &RQWURO 'DWDSDWK 0HPRU\ ,QSXW 2XWSXW e$ULWKPHWLFLQVWUXFWLRQVRSHUDQGVPXVWEHUHJLVWHUV RQO\UHJLVWHUVSURYLGHG e&RPSLOHUDVVRFLDWHVYDULDEOHVZLWKUHJLVWHUV e:KDWDERXWSURJUDPVZLWKORWVRIYDULDEOHV
Memory Organization viewed as a large, single-dimension array, with an address A memory address is an index into the array Byte addressing"means that the index points to a byte of memory 0「8 B bits of data 1「8 8 bits of data 2 8 bits of data 8 bits of data 4「8 B bits of data 8 bits of data 6「8 bits of data 北京大学计算机科学技术系 计算机系统结枃教硏室
GÜWÑÇj°_+ ÑÇj+´DÔ 0HPRU\2UJDQL]DWLRQ e 9LHZHGDVDODUJHVLQJOHGLPHQVLRQDUUD\ZLWKDQDGGUHVV e $PHPRU\DGGUHVVLVDQLQGH[LQWRWKHDUUD\ e %\WHDGGUHVVLQJPHDQVWKDWWKHLQGH[SRLQWVWR DE\WH RIPHPRU\ ELWVRIGDWD ELWVRIGDWD ELWVRIGDWD ELWVRIGDWD ELWVRIGDWD ELWVRIGDWD ELWVRIGDWD