例12数字钟设计及显示 设计要求 1、具有时、分、秒,计数及数码管 显示功能,以24小时循环计时。 2、具有清零,调节小时、分钟功能
1 例12 数字钟设计及显示 设计要求: 1、具有时、分、秒,计数及数码管 显示功能,以 24 小时循环计时。 2、具有清零,调节小时、分钟功能
实验系统箱中8位数码管的连接关系: 日H 7eg6.0] 选择信号sel[2.0]
2 实验系统箱中8位数码管的连接关系: 7seg[6..0] 选择信号 sel[2..0]
顶层设计文件: G1 MAX+plus II-h: \lecture\experiment\clock\clock- [clock. gdf- Graphic Editor A MAX+plus II Eile Edit yiew Symbol Assign Utilities Options window Help 口圖刍剧幽回炤△國囫卧為圖画图武會雷Aal SECOND o吕婴, sEc⊥3..o RESET SEc2[3.o a UX61Sc∩N CLKSCAN IN工【3,,。 H工NUTE oDT【3..o IN3【3.。】sEL[己 sEL【2.0 RESET MIN≥【3.,。 Ns【3.. HOUR SEGMENT7 DATAC3-.O DOUT 7SEG[6 圃开叫国浏览一E,xtx1…图年K可画1940
3 顶层设计文件:
秒计数设计文件: MAX+plus II-f: \ dh\mp2 \lecture\clock\second-[second, vhd- Text Editor] R MAX+plus I Ele Edt Templates Assign Utilties options window Help 口哆匈属N△囫画B感為画武會雷 Courier New,4B運 library ieee use ieee std logic 1164.alli use ieee. std logic unsigned alli entity second is port(clk, reset: in std logic secl, sec2: out std logic vector (3 downto 0)i carry: out std logic)i end secondi architecture rtl of second is signal secl t, sec2 t: std logic vectoR (3 downto o)i begin I Line 14[ Col 27 INSI
4 秒计数设计文件:
秒计数设计文件(续): WiMAX+plus II-f:\(dh(mp2 \lecture( clock(second-[second,whd-Text Editor] FR MAX+plus Il Ele Edit Iemplates Assign titles options window Help 口舀△囫郾即感囟丛盈国画国武留 ourierNew24 process(clk, reset egin if reset=1 then sec1t<="0000"; sec2t<="0000"; elsif clki event and clk=1 then if sec1 t=1001 then sec1t<="0000 if sec2 t=0101 then sec2t<="0000"; lse sec2 t<=sec2 t+li end ifi else secl t<=secl t+l I Line 14 I Col 27 INS 4I
5 秒计数设计文件(续):
秒计数设计文件(续): i9 MAX+plus lI-f: dh\mp2\lecture\clock\ second -[second. vhd- Text Editor × N MAX+plus I Ele Edit Templates Assign Utilities ptions Window Help 口倒属△國囫P画囚盈圖面雷 Courier New-1_P4 secl t<=secl t+1 end if if sec1 t=1001 and sec2 t=0101 the carry<=li lse carry<=oi end if end if secl<=sec1 t sec2<=sec2 t end processi end rtl Line43|col38|Ns」
6 秒计数设计文件(续):
分计数设计文件: DIMAX+plus II-f:\dh\mp2 Jecture \clock \minute-[minute. vhd- Text Editor] EE MAX+pus II Ele Edit Templates assign Utilties options window Help 口哆舀△國囫郾郾四囚盈圖面剧烈雷! Courier New」-B library ieee use ieeestd logic 1164.alli use ieee std logic unsignedalli entity minute is port(clk, reset: in std logici minl, min2: out std logic vector (3 downto o)i carry:out std logic)i ena minute architecture rtl of minute is signal minl ti min2 t: std logic vector 3 downto o)i begin Line 14 Col 27INS 4
7 分计数设计文件:
分计数设计文件(续): ii MAX+plus II-f:\dh\mp2\lecture \clock\minute-[minute hd-Text Editor] R MAX+plus I Ele Edt Templates Assign Utiles options Window Help ×」 process(clk reset) begi if reset=1 then min1t<="0000"; min2t<="0000"; elsif clklevent and clk=f1 then if min1 t=1001 then min1t<="0000 if min2 t=o101 then min2t<="0000"; se min2 t<=min2 t+1 end if else minl t<=minl t+l end ifi I Line 14[ Col 27 INSI
8 分计数设计文件(续):
分计数设计文件(续): 4i MAX+plus II-f: \dh\mp2 \lecture \clock \minute-[minute. vhd- Text Editor N MAX+plus II Ele Edt Templates Assign unites options window Help if minl t=l001 and min2 t=0101 then carry<=li e⊥se carry<=ori end if: end if minl<=minl t min2<=min2 ti end processi end rtl Line42|col24INs」
9 分计数设计文件(续):
小时计数设计文件 MAX+plus lI-f:\dh\mp2 \lecture\clock \minute-[hour. vhd- Text EditorI PE MAX+plus I Eile Edit Templates Assign Utilities options Window Help library ieee use ieee std logic 1164.alli use leee std logic unsigned alli entity hour is port(clk reset: in std logici hourl, hour2: out std logic vector (3 downto o))i end hour architecture rt of hour is signal hour t: std logic vector (3 downto o)i signal hour2 t: std logic vector (3 downto o)i ILine41col28Nsl」
10 小时计数设计文件: