intersi cL7106,|CL7107 /cL7106S,CL7107s 3/2 Digit January 1998 LCD/LED Display, A/D Converters Features Description Guaranteed Zero Reading for oV Input on All Scale The Intersil ICL7106 and ICL7107 are high performance, low True Polarity at Zero for Precise Null Detection power, 372 digit A/D converters. Included are seven seg- 1pA Typical Input Current ment decoders, display drivers, a reference, and a clock The ICL7106 is designed to interface with a liquid crystal dis- True Differential Input and Reference Direct Display Drive play(LCD)and includes a multiplexed backplane drive; the LCD ICL7106 LED ICL7107 ICL7107 will directly drive an instrument size light emitting Low Noise-Less Than 15uVp-p diode(LED) display The ICL7106 and ICL7107 bring together a combination of On Chip clock and Reference high accuracy, versatility, and true economy. It features auto- Low Power Dissipation- Ty pically Less Than 10mW zero to less than 10uV, zero drift of less than 1uvroC, input bias current of 10pA(Max), and rollover error of less than No Additional Active Circuits Required one count. True differential inputs and reference are useful in Enhanced Display Stability(ICL7106S, ICL7107S) all systems, but give the designer an uncommon advantage when measuring load cells, strain gauges and other bridge Ordering Information type transducers. Finally, the true economy of single power supply operation(ICL7106), enables a high performance TEMP panel meter to be built with the addition of only 10 passive PART NO.RANGE(C) PACKAGE PKG. No. components and a display 0 to 70 40 Ld PDIP E40.6 CL7106RCPL 0 to 7040 Ld PDIP(Note)E40.6 ICL7106CM44 0 to 70 44 Ld MOFP a4410×10 ICL7106SCPL 0 to 7040 Ld PDIP E40.6 ICL7107SCPL 0 to 70 40 Ld PDIP E40.6 o to 7040 Ld PDIP CL7107RCPL 0 to 7040 Ld PDIP(Note)E40.6 CL7107CM44 0 to 7044 Ld MOFP Q44.10X10 NOTE: "R"indicates device with reversed leads for mounting to PC board underside. "s" indicates enhanced stabil CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. ile number 3082.2 http://www.intersil.comor407-727-9207iCopyrighteIntersilCorporation1999
1 ICL7106, ICL7107, ICL7106S, ICL7107S 31/2 Digit, January 1998 LCD/LED Display, A/D Converters Features • Guaranteed Zero Reading for 0V Input on All Scales • True Polarity at Zero for Precise Null Detection • 1pA Typical Input Current • True Differential Input and Reference, Direct Display Drive - LCD ICL7106, LED lCL7107 • Low Noise - Less Than 15µVP-P • On Chip Clock and Reference • Low Power Dissipation - Typically Less Than 10mW • No Additional Active Circuits Required • Enhanced Display Stability (ICL7106S, ICL7107S) Description The Intersil ICL7106 and ICL7107 are high performance, low power, 31/2 digit A/D converters. Included are seven segment decoders, display drivers, a reference, and a clock. The ICL7106 is designed to interface with a liquid crystal display (LCD) and includes a multiplexed backplane drive; the ICL7107 will directly drive an instrument size light emitting diode (LED) display. The ICL7106 and ICL7107 bring together a combination of high accuracy, versatility, and true economy. It features autozero to less than 10µV, zero drift of less than 1µV/oC, input bias current of 10pA (Max), and rollover error of less than one count. True differential inputs and reference are useful in all systems, but give the designer an uncommon advantage when measuring load cells, strain gauges and other bridge type transducers. Finally, the true economy of single power supply operation (ICL7106), enables a high performance panel meter to be built with the addition of only 10 passive components and a display. Ordering Information PART NO. TEMP. RANGE (oC) PACKAGE PKG. NO. ICL7106CPL 0 to 70 40 Ld PDIP E40.6 ICL7106RCPL 0 to 70 40 Ld PDIP (Note) E40.6 ICL7106CM44 0 to 70 44 Ld MQFP Q44.10x10 ICL7106SCPL 0 to 70 40 Ld PDIP E40.6 ICL7107SCPL 0 to 70 40 Ld PDIP E40.6 ICL7107CPL 0 to 70 40 Ld PDIP E40.6 ICL7107RCPL 0 to 70 40 Ld PDIP (Note) E40.6 ICL7107CM44 0 to 70 44 Ld MQFP Q44.10x10 NOTE: “R” indicates device with reversed leads for mounting to PC board underside. “S” indicates enhanced stability. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 File Number 3082.2
cL7106,cL7107,cL7106s,|cL7107S inout ICL7106, ICL7107(PDIP) ICL7106R, ICL7107R(PDIP TOP VIEW TOP VIEW 00sc1 的9]osc2 c13 图80Sc3 OSC 33 38C1 37] TEST B1 (1s)A1[1 B6】REFH BA1}(1s) F1[6 35 REF LO EFLO 6 图F1 3 图3]cREr D2 32 COMMON COMMON 9 32D2 B1 IN HI IN LO 11 国4 A-Z 12 28BUFF 区NT 26]. G2(10s) G2(10s) 西F3(100y E3[8 (100sA3图8 (1000AB4的9 22】(1000AB4 四 BP/GND ICL7106, ICL7107(MQFP) TOP VIEW 出88 4342414039383736 Nc TESTLI OSc A的 osc2□ BP/GND ■Po D1口 IE3 c1口口 1314151 18192021
2 Pinouts ICL7106, ICL7107 (PDIP) TOP VIEW ICL7106R, ICL7107R (PDIP) TOP VIEW ICL7106, ICL7107 (MQFP) TOP VIEW 13 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 V+ D1 C1 B1 A1 F1 G1 E1 D2 C2 B2 A2 F2 E2 D3 B3 F3 E3 (1000) AB4 POL 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 OSC 1 OSC 2 OSC 3 TEST REF HI REF LO CREF+ CREFCOMMON IN HI IN LO A-Z BUFF INT V- G2 (10’s) C3 A3 G3 BP/GND (1’s) (10’s) (100’s) (MINUS) (100’s) 13 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 V+ D1 C1 B1 A1 F1 G1 E1 D2 C2 B2 A2 F2 E2 D3 B3 F3 E3 (1000) AB4 POL 28 40 39 38 37 36 35 34 33 32 31 30 29 27 26 25 24 23 22 21 OSC 1 OSC 2 OSC 3 TEST REF HI REF LO CREF+ CREFCOMMON IN HI IN LO A-Z BUFF INT V- G2 (10’s) C3 A3 G3 BP/GND (1’s) (10’s) (100’s) (MINUS) (100’s) OSC 2 NC OSC 3 TEST NC NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 OSC 1 V+ D1 C1 B1 A1 F1 G1 E1 D2 C2 28 27 26 25 24 23 18 19 20 21 22 B2 A2 F2 E2 D3 B3 F3 E3 AB4 POL BP/GND 39 38 37 36 35 34 33 32 31 30 29 44 43 42 41 40 IN HI IN LO A-Z BUFF INT V- NC G2 C3 A3 G3 REF HI REF LO CREF+ CREFCOMMON ICL7106, ICL7107, ICL7106S, ICL7107S
cL7106,cL7107,cL7106s,|cL7107S Absolute Maximum Ratings Thermal Information Supply Voltage Thermal Resistance(Typical, Note 2) 0JA CCM) ICL7106. V+ to v- PDIP Package ICL7107. V+ to GND 6 ICL7107.V-to GND -9v Maximum Junction Temperature Analog Input voltage(Either Input)(Note 1) V+ to V- Maximum Storage Temperature Range -65°cto150° Reference Input Voltage(Either Input) V+ to V- Maximum Lead Temperature(Soldering 10s) Clock Input MQFP-Lead Tips Only CL7106 TEST to V+ ICL71 Operating Conditions Temperature Range 0cto7o°c CAUTION: Stresses above those listed in Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation the device at these or any other conditions above those indicated in the operational sections of this specification is not implied NOTES: ut current Is 2. BJA is measured with the component mounted on an evaluation PC board in free air Electrical Specifications ( Note 3) PARAMETER TEST CONDITIONS TYP MAX UNIT SYSTEM PERFORMANCE Zero Input Reading VIN=0.0V, Full Scale= 200mV 0000±0000+0000 Digital Stability(Last Digit)(ICL7106S, ICL7107s Fixed Input Voltage( Note 7) 000d0000000gita Ratiometric Reading VIN= VREF, VREF =100mV 999999/101000 Rollover Errol Difference in Reading for Equal Positive and Negative Inputs Near Full Scale Linearity Full scale 200mv or Full scale 2V Maximum ±0.2 Counts Deviation from Best Straight Line Fit(Note 6) Common Mode Rejection Ratio CM=1V, VIN=OV, Full Scale 200mV(Note 6) ViN=oV, Full Scale= 200mV 15 ( Peak-To-Peak value Not Exceeded 95% of Time) Leakage] Input VIN =0(Note 6) 10 pA Zero Reading Drift VN=0,0°cTo70°c(Note6) Scale Factor Temperature Coefficient VN=199mV,0°cTo70°c, ppmn°c ( Ext. Ref0ppm/°C) End Power Supply Character V+ Supply VIN=O(Does Not Indlude LED Current for ICL7107) 1.0 18 mA Current End Power Supply Character V Supply Current ICL7107 Only 0618 COMMON Pin Analog Common Voltage Temperature Coefficient of Analog Common 25kQ2 Between DISPLAY DRIVER ICL7106 ONLY Peak-To-Peak Segment Drive Voltage V+= to v-= 9v(Note 5) 5.5 Peak-To-Peak Backplane Drive Voltage
3 Absolute Maximum Ratings Thermal Information Supply Voltage ICL7106, V+ to V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V ICL7107, V+ to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V ICL7107, V- to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-9V Analog Input Voltage (Either Input) (Note 1). . . . . . . . . . . . . V+ to VReference Input Voltage (Either Input) . . . . . . . . . . . . . . . . . V+ to VClock Input ICL7106 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TEST to V+ ICL7107 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .GND to V+ Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to 70oC Thermal Resistance (Typical, Note 2) θJA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (MQFP - Lead Tips Only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Input voltages may exceed the supply voltages provided the input current is limited to ±100µA. 2. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications (Note 3) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SYSTEM PERFORMANCE Zero Input Reading VIN = 0.0V, Full Scale = 200mV -000.0 ±000.0 +000.0 Digital Reading Stability (Last Digit) (ICL7106S, ICL7107S Only) Fixed Input Voltage (Note 7) -000.0 ±000.0 +000.0 Digital Reading Ratiometric Reading VlN = VREF, VREF = 100mV 999 999/10 00 1000 Digital Reading Rollover Error -VIN = +VlN ≅ 200mV Difference in Reading for Equal Positive and Negative Inputs Near Full Scale - ±0.2 ±1 Counts Linearity Full Scale = 200mV or Full Scale = 2V Maximum Deviation from Best Straight Line Fit (Note 6) - ±0.2 ±1 Counts Common Mode Rejection Ratio VCM = 1V, VIN = 0V, Full Scale = 200mV (Note 6) - 50 - µV/V Noise VIN = 0V, Full Scale = 200mV (Peak-To-Peak Value Not Exceeded 95% of Time) - 15 - µV Leakage Current Input VlN = 0 (Note 6) - 1 10 pA Zero Reading Drift VlN = 0, 0oC To 70oC (Note 6) - 0.2 1 µV/oC Scale Factor Temperature Coefficient VIN = 199mV, 0oC To 70oC, (Ext. Ref. 0ppm/oC) (Note 6) - 1 5 ppm/oC End Power Supply Character V+ Supply Current VIN = 0 (Does Not Include LED Current for ICL7107) - 1.0 1.8 mA End Power Supply Character V- Supply Current ICL7107 Only - 0.6 1.8 mA COMMON Pin Analog Common Voltage 25kΩ Between Common and Positive Supply (With Respect to + Supply) 2.4 3.0 3.2 V Temperature Coefficient of Analog Common 25kΩ Between Common and Positive Supply (With Respect to + Supply) - 80 - ppm/oC DISPLAY DRIVER ICL7106 ONLY Peak-To-Peak Segment Drive Voltage Peak-To-Peak Backplane Drive Voltage V+ = to V- = 9V (Note 5) 4 5.5 6 V ICL7106, ICL7107, ICL7106S, ICL7107S
cL7106,cL7107,cL7106s,|cL7107S Electrical Specifications (Note 3)(Continued) PARAMETER TEST CONDITIONS TYP MAX UNIT DISPLAY DRIVER ICL7107 ONLY Segment Sinking Current V+=5v, Segment Voltage 3V Except Pins 19 and 20) 8 Pin 19 Only AAA Pin 20 Only NOTES: 3. Dissipation rating assumes device is mounted with all leads soldered to printed circuit board 4. Unless otherwise noted, specifications apply to both the ICL7106 and ICL7107 at Ta= 25C, fcLOCK = 48kHZ. ICL7106 is tested in the circuit of Figure 1. ICL7107 is tested in the circuit of Figure 2. 5. Back plane drive is in phase with segment drive for ' off segment, 180 degrees out of phase for on segment. Frequency is 20 times conversion rate. Average DC component is less than 50mv. 6. Not tested, guaranteed by design 7. Sample Tested Typical Applications and Test Circuits c1=0.1F c2=047F §惠}呈“盖呈B323B cL7106 s百5百6面88 N2 9 M? R3=100k E回囟西回回回回图图巴图图 R5=1M 999 FIGURE 1. ICL7106 TEST CIRCUIT AND TYPICAL APPLICATION WITH LCD DISPLAY COMPONENTS SELECTED FOR 200mV FULL SCALE §§号要呈言 左888 cL710 Eδ西6西888a DISPLAY E/999 FIGURE 2. ICL7107 TEST CIRCUIT AND TYPICAL APPLICATION WITH LED DISPLAY COMPONENTS SELECTED FOR 200mV FULL SCALE
4 Typical Applications and Test Circuits DISPLAY DRIVER ICL7107 ONLY Segment Sinking Current V+ = 5V, Segment Voltage = 3V (Except Pins 19 and 20) 5 8 - mA Pin 19 Only 10 16 - mA Pin 20 Only 4 7 - mA NOTES: 3. Dissipation rating assumes device is mounted with all leads soldered to printed circuit board. 4. Unless otherwise noted, specifications apply to both the ICL7106 and ICL7107 at TA = 25oC, fCLOCK = 48kHz. ICL7106 is tested in the circuit of Figure 1. ICL7107 is tested in the circuit of Figure 2. 5. Back plane drive is in phase with segment drive for ‘off’ segment, 180 degrees out of phase for ‘on’ segment. Frequency is 20 times conversion rate. Average DC component is less than 50mV. 6. Not tested, guaranteed by design. 7. Sample Tested. Electrical Specifications (Note 3) (Continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT FIGURE 1. ICL7106 TEST CIRCUIT AND TYPICAL APPLICATION WITH LCD DISPLAY COMPONENTS SELECTED FOR 200mV FULL SCALE FIGURE 2. ICL7107 TEST CIRCUIT AND TYPICAL APPLICATION WITH LED DISPLAY COMPONENTS SELECTED FOR 200mV FULL SCALE 13 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 V+ D1 C1 B1 A1 F1 G1 E1 D2 C2 B2 A2 F2 E2 D3 B3 F3 E3 AB4 POL OSC 1 OSC 2 OSC 3 TEST REF HI REF LO CREF+ CREFCOM IN HI IN LO A-Z BUFF INT V- G2 C3 A3 G3 BP DISPLAY DISPLAY C1 C2 C3 C4 R3 R1 R4 C5 + - IN R5 R2 9V ICL7106 C1 = 0.1µF C2 = 0.47µF C3 = 0.22µF C4 = 100pF C5 = 0.02µF R1 = 24kΩ R2 = 47kΩ R3 = 100kΩ R4 = 1kΩ R5 = 1MΩ + - 13 1 2 3 4 5 6 7 8 9 10 11 12 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 V+ D1 C1 B1 A1 F1 G1 E1 D2 C2 B2 A2 F2 E2 D3 B3 F3 E3 AB4 POL OSC 1 OSC 2 OSC 3 TEST REF HI REF LO CREF+ CREFCOM IN HI IN LO A-Z BUFF INT V- G2 C3 A3 G3 GND DISPLAY DISPLAY C1 C2 C3 C4 R3 R1 R4 C5 + - IN R5 R2 ICL7107 +5V -5V C1 = 0.1µF C2 = 0.47µF C3 = 0.22µF C4 = 100pF C5 = 0.02µF R1 = 24kΩ R2 = 47kΩ R3 = 100kΩ R4 = 1kΩ R5 = 1MΩ ICL7106, ICL7107, ICL7106S, ICL7107S
cL7106,cL7107,cL7106s,|cL7107S Design Information Summary Sheet OSCILLATOR FREQUENCY · DISPLAY COUNT fosc =0.45/RC COUNT=1000XV Cosc >50pF: Rosc > 50k fosc(Typ)=48kHz CONVERSION CYCLE · OSCILLATOR PERIOD tcyc =tCLOCK X 4000 Rc045 tcyc =tosc X 16,000 INTEGRATION CLOCK FREQUENCY when fosc =48kHz; tcYC =333ms COMMON MODE INPUT VOLTAGE c+1V)<VN<(+-0.5V) INTEGRATION PERIOD · AUTO-ZERO CAPACITOR tINT 1000 X(4/fosc 60/50Hz REJECTION CRITERION REFERENCE CAPACITOR tINT/60Hz Or tIN 0. 1uF CREF luF OPTIMUM INTEGRATION CURRENT v INT =4 Biased between Vi and V- FULL SCALE ANALOG INPUT VOLTAGE vcoM≡V+28V VINFS (TyP)=200mV or 2V Regulation lost when V+to∨<≡6.8V If VcoM is externally pulled down to(V+ to v-)/2, INTEGRATE RESISTOR he VcoM circuit will turn off R INT ICL7106 POWER SUPPLY: SINGLE 9V V+-V-=9V · INTEGRATE CAPACITOR Digital supply is generated internally (INT)(INT) VGND=V+-4.5V ICL7106 DISPLAY: LCD INTEGRATOR OUTPUT VOLTAGE SWING (tINT)(INT) ICL7107 POWER SUPPLY: DUAl V+=+5V to GND V-=-5V to GND VINT MAXIMUM SWING: Digital Logic and LED driver supply V+ to GND +05V)<VNT<0+-0.5v),VNT(Typ)=2V ICL7107 DISPLAY: LED Type: Non-Multiplexed Common Anode Typical Integrator Amplifier output Waveform(INT Pin 2③-微 ToTAL CONVERSION TIME=4000 x clocK =16,000 x tosc
5 Typical Integrator Amplifier Output Waveform (INT Pin) Design Information Summary Sheet • OSCILLATOR FREQUENCY fOSC = 0.45/RC COSC > 50pF; ROSC > 50kΩ fOSC (Typ) = 48kHz • OSCILLATOR PERIOD tOSC = RC/0.45 • INTEGRATION CLOCK FREQUENCY fCLOCK = fOSC/4 • INTEGRATION PERIOD tINT = 1000 x (4/fOSC) • 60/50Hz REJECTION CRITERION tINT/t60Hz or tlNT/t60Hz = Integer • OPTIMUM INTEGRATION CURRENT IINT = 4µA • FULL SCALE ANALOG INPUT VOLTAGE VlNFS (Typ) = 200mV or 2V • INTEGRATE RESISTOR • INTEGRATE CAPACITOR • INTEGRATOR OUTPUT VOLTAGE SWING • VINT MAXIMUM SWING: (V- + 0.5V) < VINT < (V+ - 0.5V), VINT (Typ) = 2V • DISPLAY COUNT • CONVERSION CYCLE tCYC = tCL0CK x 4000 tCYC = tOSC x 16,000 when fOSC = 48kHz; tCYC = 333ms • COMMON MODE INPUT VOLTAGE (V- + 1V) < VlN < (V+ - 0.5V) • AUTO-ZERO CAPACITOR 0.01µF < CAZ < 1µF • REFERENCE CAPACITOR 0.1µF < CREF < 1µF • VCOM Biased between Vi and V-. • VCOM ≅ V+ - 2.8V Regulation lost when V+ to V- < ≅6.8V If VCOM is externally pulled down to (V+ to V-)/2, the VCOM circuit will turn off. • ICL7106 POWER SUPPLY: SINGLE 9V V+ - V- = 9V Digital supply is generated internally VGND ≅ V+ - 4.5V • ICL7106 DISPLAY: LCD Type: Direct drive with digital logic supply amplitude. • ICL7107 POWER SUPPLY: DUAL ±5.0V V+ = +5V to GND V- = -5V to GND Digital Logic and LED driver supply V+ to GND • ICL7107 DISPLAY: LED Type: Non-Multiplexed Common Anode RINT VINFS I INT = ----------------- CINT t INT ( ) I INT ( ) VINT = -------------------------------- VINT t INT ( ) I INT ( ) CINT = -------------------------------- COUNT 1000 VIN VREF = × --------------- AUTO ZERO PHASE (COUNTS) 2999 - 1000 SIGNAL INTEGRATE PHASE FIXED 1000 COUNTS DE-INTEGRATE PHASE 0 - 1999 COUNTS TOTAL CONVERSION TIME = 4000 x tCLOCK = 16,000 x tOSC ICL7106, ICL7107, ICL7106S, ICL7107S
cL7106,cL7107,cL7106s,|cL7107S Detailed Description the end of this phase, the polarity of the integrated signal is determined Analog Section De-integrate Phase Figure 3 shows the Analog Section for the ICL7106 and ICL7107. Each measurement cycle is divided into three The final phase is de-integrate, or reference integrate Input phases. They are(1)auto-zero(A-Z),(2)signal integrate low is internally connected to analog COMMON and input (INT) and (3)de- integrate(DE) high is connected across the previously charged reference capacitor. Circuitry within the chip ensures that the capacitor Auto-Zero phase will be connected with the correct polarity to cause the During auto-zero three things happen First, input high and integrator output to return to zero. The time required for the low are disconnected from the pins and internally shorted to output to return to zero is proportional to the input signal analog COMMON. Second, the reference capacitor is Specifically the digital reading displayed charged to the reference voltage. Third, a feedback loop closed around the system to charge the auto-zero capacitor DISPLAY COUNT= 1000 REF) CAz to compensate for offset voltages in the buffer amplifier integrator, and comparator. Since the comparator is included in the loop, the A-z accuracy is limited only by the noise of Differential Input the system. In any case, the offset referred to the input is less than 10uV The input can accept differential voltages anywhere within the common mode range of the input amplifier, or specifically from Signal Integrate Phase 0.5v below the positive supply to 1V above the negative sup- ply. In this range, the system has a CMRR of 86dB typical internal short is removed, and the internal input high and low put does not saturate. A worst case condition would be a large are connected to the external pins. The converter then positive common mode voltage with a near full scale negative integrates the differential voltage between IN HI and IN lo differential input voltage. The negative input signal drives the for a fixed time. This differential voltage can be within a wide integrator positive when most of its swing has been used up ommon mode range: up to 1V from either supply. If, on the by the positive common mode voltage. For these critical appli other hand, the input signal has no return with respect to the cations the integrator output swing can be reduced to less converter power supply LO can be tied to analog than the recommended 2V full scale swing with little loss of COMMON to establish the correct common mode voltage At accuracy The integrator output can swing to within 0.3v of either supply without loss of linearity STRAY STRAY cREF↓REFH REF LO↓cREF BUFFER A-Z X A-z INTEGRATOR 2.8v TION IN HI DE 6.2V HIGH COMPARATOR COMMON INT A-Z AND DE(出 LOW N LO FIGURE 3. ANALOG SECTION OF ICL7106 AND ICL710
6 Detailed Description Analog Section Figure 3 shows the Analog Section for the ICL7106 and ICL7107. Each measurement cycle is divided into three phases. They are (1) auto-zero (A-Z), (2) signal integrate (INT) and (3) de-integrate (DE). Auto-Zero Phase During auto-zero three things happen. First, input high and low are disconnected from the pins and internally shorted to analog COMMON. Second, the reference capacitor is charged to the reference voltage. Third, a feedback loop is closed around the system to charge the auto-zero capacitor CAZ to compensate for offset voltages in the buffer amplifier, integrator, and comparator. Since the comparator is included in the loop, the A-Z accuracy is limited only by the noise of the system. In any case, the offset referred to the input is less than 10µV. Signal Integrate Phase During signal integrate, the auto-zero loop is opened, the internal short is removed, and the internal input high and low are connected to the external pins. The converter then integrates the differential voltage between IN HI and IN LO for a fixed time. This differential voltage can be within a wide common mode range: up to 1V from either supply. If, on the other hand, the input signal has no return with respect to the converter power supply, IN LO can be tied to analog COMMON to establish the correct common mode voltage. At the end of this phase, the polarity of the integrated signal is determined. De-Integrate Phase The final phase is de-integrate, or reference integrate. Input low is internally connected to analog COMMON and input high is connected across the previously charged reference capacitor. Circuitry within the chip ensures that the capacitor will be connected with the correct polarity to cause the integrator output to return to zero. The time required for the output to return to zero is proportional to the input signal. Specifically the digital reading displayed is: . Differential Input The input can accept differential voltages anywhere within the common mode range of the input amplifier, or specifically from 0.5V below the positive supply to 1V above the negative supply. In this range, the system has a CMRR of 86dB typical. However, care must be exercised to assure the integrator output does not saturate. A worst case condition would be a large positive common mode voltage with a near full scale negative differential input voltage. The negative input signal drives the integrator positive when most of its swing has been used up by the positive common mode voltage. For these critical applications the integrator output swing can be reduced to less than the recommended 2V full scale swing with little loss of accuracy. The integrator output can swing to within 0.3V of either supply without loss of linearity. DISPLAY COUNT = 1000 VIN VREF --------------- FIGURE 3. ANALOG SECTION OF ICL7106 AND ICL7107 DE+ DECAZ CINT RINT BUFFER A-Z INT - + A-Z COMPARATOR IN HI COMMON IN LO 31 32 30 INT DE- DE+ A-Z 34 CREF+ 36 REF HI CREF REF LO 35 A-Z A-Z 33 CREF- 28 29 27 TO DIGITAL SECTION A-Z AND DE(±) INTEGRATOR INT STRAY STRAY V+ 10µA V- N INPUT HIGH 2.8V 6.2V V+ 1 INPUT LOW - + - + - + ICL7106, ICL7107, ICL7106S, ICL7107S
cL7106,cL7107,cL7106s,|cL7107S Differential Reference should be since this removes the common mode voltage he reference voltage can be generated anywhere within the om the reference system power supply voltage of the converter. The main source of com- Within the IC, analog CoMMON is tied to an N-Channel FET mon mode error is a roll-over voltage caused by the reference that can sink approximately 30mA of current to hold the capacitor losing or gaining charge to stray capacity on its voltage 2.8v below the positive supply(when a load is trying nodes. If there is a large common mode voltage, the reference to pull the common line positive). However, there is only capacitor can gain charge(increase voltage) when called up to 10uA of source current, so CoMMon may easily be tied to a de-integrate a positive signal but lose charge(decrease volt- more negative voltage thus overriding the internal reference. age)when called up to de- integrate a negative input signal This difference in reference for positive or negative input voltage will give a roll-over eror. However, by selecting the reference capacitor such that it is large enough in comparison to the stray capacitance, this emor can be held to less than 0.5 count worst REF HI case(See Component Value Selection. REF LO Analog COMMON This pin is included primarily to set the common mode cL7106 voltage for battery operation(ICL7106) or for any system where the input signals are fioating with respect to the power supply. The COMMON pin sets a voltage that is approxi mately 2.8V more negative than the positive supply. This is elected to give a minimum end-of-life battery voltage of FIGURE 4A about 6V. However, analog CoMMon has some of the attributes of a reference voltage. When the total supply voltage is large enough to cause the zener to regulate(7V), the COMMON voltage will have a low voltage coefficient (0.001%/), low output impedance =1592), and a 6.8kQ temperature coefficient typically less than 80ppm/oc cL7106 The limitations of the on chip reference should also be REF HI L8069 recognized, however. With the ICL7107, the internal heating which results from the led drivers can cause some REF LO degradation in performance Due to their higher thermal resis- tance, plastic parts are poorer in this respect than ceramic. The combination of reference Temperature Coefficient (TC) internal chip dissipation, and package thermal resistance can FIGURE 4B increase noise near full scale from 25uV to 80uVp-P FIGURE 4. USING AN EXTERNAL REFERENCE inearity in going from a high dissipation count such as 1000 20 segments on)to a low dissipation count such as 1111(8 teST segments on) can suffer by a count or more. Devices with a positive TC reference may require several counts to pull out of The TEST pin serves two functions. On the ICL7106 it is an over-range condition This is because over-range is a low coupled to the internally generated digital supply through dissipation mode, with the three least significant digits 5002 resistor. Thus it can be used as the negative supply for blanked.Similarly, units with a negative Tc may cycle externally generated segment drivers such as decimal points between over-range and a non-over-range count as the die or any other presentation the user may want to include on alternately heats and cools. All these problems are of course the LCd display. Figures 5 and 6 show such an application eliminated if an external reference is used No more than a 1mA load should be applie The ICL7106, with its negligible dissipation, suffers from none of these problems. In either case, an external reference can easily be added, as shown in Figure 4 1MQ Analog COMMON is also used as the input low return duri auto-zero and de-integrate. If IN LO is different from anal COMMON, a common mode voltage exists in the cL710 nd is taken care of by the excellent CmRR of the cor However, in some applications IN LO will be set at known voltage(power supply common for instance). In this application, analog COMMON should be tied to the same TEST point, thus removing from th converter. The same holds true for the reference voltage. If eference can be conveniently tied to analog COMMON, it FIGURE 5. SIMPLE INVERTER FOR FIXED DECIMAL POINT
7 Differential Reference The reference voltage can be generated anywhere within the power supply voltage of the converter. The main source of common mode error is a roll-over voltage caused by the reference capacitor losing or gaining charge to stray capacity on its nodes. If there is a large common mode voltage, the reference capacitor can gain charge (increase voltage) when called up to de-integrate a positive signal but lose charge (decrease voltage) when called up to de-integrate a negative input signal. This difference in reference for positive or negative input voltage will give a roll-over error. However, by selecting the reference capacitor such that it is large enough in comparison to the stray capacitance, this error can be held to less than 0.5 count worst case. (See Component Value Selection.) Analog COMMON This pin is included primarily to set the common mode voltage for battery operation (ICL7106) or for any system where the input signals are floating with respect to the power supply. The COMMON pin sets a voltage that is approximately 2.8V more negative than the positive supply. This is selected to give a minimum end-of-life battery voltage of about 6V. However, analog COMMON has some of the attributes of a reference voltage. When the total supply voltage is large enough to cause the zener to regulate (>7V), the COMMON voltage will have a low voltage coefficient (0.001%/V), low output impedance (≅15Ω), and a temperature coefficient typically less than 80ppm/oC. The limitations of the on chip reference should also be recognized, however. With the ICL7107, the internal heating which results from the LED drivers can cause some degradation in performance. Due to their higher thermal resistance, plastic parts are poorer in this respect than ceramic. The combination of reference Temperature Coefficient (TC), internal chip dissipation, and package thermal resistance can increase noise near full scale from 25µV to 80µVP-P. Also the linearity in going from a high dissipation count such as 1000 (20 segments on) to a low dissipation count such as 1111(8 segments on) can suffer by a count or more. Devices with a positive TC reference may require several counts to pull out of an over-range condition. This is because over-range is a low dissipation mode, with the three least significant digits blanked. Similarly, units with a negative TC may cycle between over-range and a non-over-range count as the die alternately heats and cools. All these problems are of course eliminated if an external reference is used. The ICL7106, with its negligible dissipation, suffers from none of these problems. In either case, an external reference can easily be added, as shown in Figure 4. Analog COMMON is also used as the input low return during auto-zero and de-integrate. If IN LO is different from analog COMMON, a common mode voltage exists in the system and is taken care of by the excellent CMRR of the converter. However, in some applications IN LO will be set at a fixed known voltage (power supply common for instance). In this application, analog COMMON should be tied to the same point, thus removing the common mode voltage from the converter. The same holds true for the reference voltage. If reference can be conveniently tied to analog COMMON, it should be since this removes the common mode voltage from the reference system. Within the lC, analog COMMON is tied to an N-Channel FET that can sink approximately 30mA of current to hold the voltage 2.8V below the positive supply (when a load is trying to pull the common line positive). However, there is only 10µA of source current, so COMMON may easily be tied to a more negative voltage thus overriding the internal reference. TEST The TEST pin serves two functions. On the ICL7106 it is coupled to the internally generated digital supply through a 500Ω resistor. Thus it can be used as the negative supply for externally generated segment drivers such as decimal points or any other presentation the user may want to include on the LCD display. Figures 5 and 6 show such an application. No more than a 1mA load should be applied. FIGURE 4A. FIGURE 4B. FIGURE 4. USING AN EXTERNAL REFERENCE ICL7106 V REF LO ICL7107 REF HI V+ V- 6.8V ZENER IZ ICL7106 V REF HI REF LO COMMON V+ ICL8069 1.2V REFERENCE 6.8kΩ 20kΩ ICL7107 ICL7106 V+ BP TEST 21 37 TO LCD BACKPLANE TO LCD DECIMAL POINT 1MΩ FIGURE 5. SIMPLE INVERTER FOR FIXED DECIMAL POINT ICL7106, ICL7107, ICL7106S, ICL7107S
cL7106,cL7107,cL7106s,|cL7107S The second function is a"lamp test. When TEST is pulled Digital Section high(to V+)all segments will be turned on and the display should read1888". The TEST pin will sink about 15ma Figures 7 and 8 show the digital section for the ICL7106 and under these conditions ICL7107, respectively. In the ICL7106, an internal digital voltage(no square-wave). This may burn the LCD display int Dc ground is generated from a 6V Zener diode and a large P-Channel source follower. This supply is made stiff to plane(BP) voltage is switched. The BP frequency is the clock frequency divided by 800. For three readings/sec., this is a 60Hz square wave with a nominal amplitude of 5V. the egments are driven at the same frequency and amplitude and are in phase with BP when OF F, but out of phase when ON. In all cases negligible DC voltage exists across the ICL7106 DECIMAL Figure 8 is the Digital Section of the ICL7107. It is identical SELECT to the ICL7106 except that the regulated supply and back plane drive have been eliminated and the segment drive has TEST been increased from 2mA to 8mA, typical for instrument size cD4030 AGND common anode LEd displays. Since the 1000 output(pin 19) must sink current from two LED segments, it has twice the drive capability or 16mA. FIGURE 6. EXCLUSIVE ' GATE FOR DECIMAL POINT DRIVE In both devices, the polarity indication is"on"for negative analog inputs. If IN LO and IN HI are reversed, this indication B5579 BACKPLANE ------}- LCD PHASE DRIVER TYPICAL SEGMENT OUTPUT DECODE II DECODE II DECODE ■■■ ■■■ GMEN LATCH COUNTER ICOUNTERCOUNTERCOUNTER INTERNAL DIGITAL GROUN TO SWITCH DRIVERS FROM COMPARATOR OUTPUT CLOCK LOGIC CoNTR THREE INVERTERS TEST ONE INVERTER SHOWN FOR CLARITY OSC 2
8 The second function is a “lamp test”. When TEST is pulled high (to V+) all segments will be turned on and the display should read “1888”. The TEST pin will sink about 15mA under these conditions. CAUTION: In the lamp test mode, the segments have a constant DC voltage (no square-wave). This may burn the LCD display if maintained for extended periods. Digital Section Figures 7 and 8 show the digital section for the ICL7106 and ICL7107, respectively. In the ICL7106, an internal digital ground is generated from a 6V Zener diode and a large P-Channel source follower. This supply is made stiff to absorb the relative large capacitive currents when the back plane (BP) voltage is switched. The BP frequency is the clock frequency divided by 800. For three readings/sec., this is a 60Hz square wave with a nominal amplitude of 5V. The segments are driven at the same frequency and amplitude and are in phase with BP when OFF, but out of phase when ON. In all cases negligible DC voltage exists across the segments. Figure 8 is the Digital Section of the ICL7107. It is identical to the ICL7106 except that the regulated supply and back plane drive have been eliminated and the segment drive has been increased from 2mA to 8mA, typical for instrument size common anode LED displays. Since the 1000 output (pin 19) must sink current from two LED segments, it has twice the drive capability or 16mA. In both devices, the polarity indication is “on” for negative analog inputs. If IN LO and IN HI are reversed, this indication can be reversed also, if desired. ICL7106 V+ BP TEST DECIMAL POINT SELECT CD4030 GND V+ TO LCD DECIMAL POINTS FIGURE 6. EXCLUSIVE ‘OR’ GATE FOR DECIMAL POINT DRIVE 7 SEGMENT DECODE SEGMENT OUTPUT 0.5mA 2mA INTERNAL DIGITAL GROUND TYPICAL SEGMENT OUTPUT V+ LCD PHASE DRIVER LATCH 7 SEGMENT DECODE ÷200 LOGIC CONTROL INTERNAL VTH = 1V 7 SEGMENT DECODE 1000’s 100’s 10’s 1’s TO SWITCH DRIVERS FROM COMPARATOR OUTPUT DIGITAL GROUND ÷4 CLOCK 40 39 38 OSC 1 OSC 2 OSC 3 BACKPLANE 21 V+ TEST V- 500Ω 37 26 6.2V COUNTER COUNTER COUNTER COUNTER 1 c a b c d f g e a b a b c d f g e a b c d f g e † † THREE INVERTERS ONE INVERTER SHOWN FOR CLARITY FIGURE 7. ICL7106 DIGITAL SECTION ICL7106, ICL7107, ICL7106S, ICL7107S
cL7106,cL7107,cL7106s,|cL7107S B35579 E团 DECODE ■■■ 口■■ TYPICAL SEGMENT OUTPUT ■■ LATCH SEGMENT UNTER COUNTERCOUNTERCOUNTER TO SWITCH DRIVERS DIGITAL GROUND FROM COMPARATOR OUTPUT CLOCK TEST 4+ LOGIC CONTROI 5009 TTHREE INV DIGITAL ONE INVERT HOWN FOR CLARITY OSc 2 OSC 3 FIGURE 8. ICL7107 DIGITAL SECTION stem Timing NTERNAL TO PART Figure 9 shows the clocking arrangement used in the ICL7106 and ICL7107. Two basic clocking arrangements CLOCK can be used 1. Figure 9A. An external oscillator connected to pin 40 2. Figure 9B. An R-C oscillator using all three pins The oscillator frequency is divided by four before it clocks the decade counters. It is then further divided to form the three convert-cycle phases. These are signal integrate (1000 TEST ICL7106 counts), reference de- integrate (0 to 2000 counts) and FIGURE 9A auto-zero(1000 to 3000 counts). For signals less than full scale, auto-zero gets the unused portion of reference de-integrate. This makes a complete measure cycle of 4, 000 :INTERNAL TO PART For three readings/second, an oscillator frequency of 48kHz CLOCK ould be used integrate cycle should be a multiple of 60HZ. Oscillator I frequencies of 240KHz, 120kHz, 80kHz, 60kHz, 48kHz, 9 40kHz, 33/3kHz, etc. should be selected For 50Hz rejec tion, Oscillator frequencies of 200kHz, 100kHz, 66/3KHz, le. Note that 40kHZ(2.5 RC OSCILLATOR FIGURE 9B FIGURE 9. CLOCK CIRCUITS
9 System Timing Figure 9 shows the clocking arrangement used in the ICL7106 and ICL7107. Two basic clocking arrangements can be used: 1. Figure 9A. An external oscillator connected to pin 40. 2. Figure 9B. An R-C oscillator using all three pins. The oscillator frequency is divided by four before it clocks the decade counters. It is then further divided to form the three convert-cycle phases. These are signal integrate (1000 counts), reference de-integrate (0 to 2000 counts) and auto-zero (1000 to 3000 counts). For signals less than full scale, auto-zero gets the unused portion of reference de-integrate. This makes a complete measure cycle of 4,000 counts (16,000 clock pulses) independent of input voltage. For three readings/second, an oscillator frequency of 48kHz would be used. To achieve maximum rejection of 60Hz pickup, the signal integrate cycle should be a multiple of 60Hz. Oscillator frequencies of 240kHz, 120kHz, 80kHz, 60kHz, 48kHz, 40kHz, 331/3kHz, etc. should be selected. For 50Hz rejection, Oscillator frequencies of 200kHz, 100kHz, 662/3kHz, 50kHz, 40kHz, etc. would be suitable. Note that 40kHz (2.5 readings/second) will reject both 50Hz and 60Hz (also 400Hz and 440Hz). 7 SEGMENT DECODE TO SEGMENT 0.5mA 8mA DIGITAL GROUND TYPICAL SEGMENT OUTPUT V+ LATCH 7 SEGMENT DECODE LOGIC CONTROL 7 SEGMENT DECODE 1000’s 100’s 10’s 1’s TO SWITCH DRIVERS FROM COMPARATOR OUTPUT DIGITAL GROUND ÷4 CLOCK 40 39 38 OSC 1 OSC 2 OSC 3 V+ TEST 500Ω COUNTER COUNTER COUNTER COUNTER 1 V+ 37 27 c a b c d f g e a b a b c d f g e a b c d f g e † † THREE INVERTERS ONE INVERTER SHOWN FOR CLARITY FIGURE 8. ICL7107 DIGITAL SECTION CLOCK INTERNAL TO PART 40 39 38 GND ICL7107 ÷4 CLOCK INTERNAL TO PART 40 39 38 ÷4 RC OSCILLATOR R C TEST ICL7106 FIGURE 9B. FIGURE 9. CLOCK CIRCUITS FIGURE 9A. ICL7106, ICL7107, ICL7106S, ICL7107S
cL7106,cL7107,cL7106s,|cL7107S Component value Selection Reference Voltage Integrating Resistor The analog input required to generate full scale output(2000 counts)is: VIN= 2VREF. Thus, for the 200mV and 2V scale, Both the buffer amplifier and the integrator have a class a VREF should equal 100mV and 1V, respectively. However, in output stage with 100uA of quiescent current. They can many applications where the AD is connected to a upply 4uA of drive current with negligible nonlinearity. The transducer, there will exist a scale factor other than unity integrating resistor should be large enough to remain in this between the input voltage and the digital reading.For very linear region over the input voltage range, but small instance, in a weighing system, the designer might like to enough that undue leakage requirements are not placed have a scale reading when the voltage from the the PC board For 2V full scale, 470kQ2 is near optimum and transducer is 0.662V. Instead of dividing the input down to similarly a 47kQ2 for a 200mV scale 200mv, the designer should use the input voltage directly Integrating Capacitor and select VREF =0.341V. Suitable values for integrating resistor and capacitor would be 1 20k@2 and 0.22uF. This The integrating capacitor should be selected to give the makes the system slightly quieter and also avoids a divider maximum voltage swing that ensures tolerance buildup will network on the input The ICL7107 with +5V supplies can not saturate the integrator swing(approximately 0.3V from accept input signals up to +4V. Another advantage of this either supply). In the ICL7106 or the ICL7107, when the system occurs when a digital reading of zero is desired for analog COMMON is used as a reference, a nominal +2V full- VIN#O Temperature and weighing systems with a variable scale integrator swing is fine. For the ICL7107 with +5v fare are examples. This offset reading can be conveniently supplies and analog COMMON tied to supply ground, a generated by connecting the voltage transducer between IN +3.5v to +4V swing is nominal. For three readings/second HI and COMMON and the variable(or fixed) offset voltage (48kHz clock) nominal values for Cint are 0.22uF and between COMMON and IN LO 0. 10uF, respectively. Of course, if different oscillator frequen- cies are used, these values should be changed in inverse ICL7107 Power Supplies proportion to maintain the same output swing The ICL7107 is designed to work from +5V supplies. An additional requirement of the integrating capacitor is that However, if a negative supply is not available, it can be errors. While other types of capacitors are adequate for this and an inexpensive IC. Figure 10 shows this application. See application, polypropylene capacitors give undetectable ICL7660 data sheet for an alternative. errors In fact, in selected applications no negative supply is Auto-Zero Capacitor quired. The conditions to use a single +5V supply he size of the auto-zero capacitor has some influence on 1. The input signal can be referenced to the center of the the noise of the system For 200mv full scale where noise is common mode range of the converter very important, a 0. 47uF capacitor is recommended On the 2. The signal is less than +1.5 2V scale, a 0.047uF capacitor increases the speed of recov- 3. An external reference is used ery from overload and is adequate for noise on this scal Reference Capacitor A0.1 tor gives good results in most applications. V+o- a large common mode voltage exists(i.e the REF LO pin is not at analog COMMON) and a 200mV scale is used, a larger value is required to prevent roll-over error. Generally 1uF will hold the roll-over error to 0.5 count OSc 1 I IN914 Oscillator Components For all ranges of frequency a 100kQ2 resistor is recommende cL7107 and the capacitor is selected from the equation GND f =o For 48kHz Clock(3 Readings/sec), C= 100pF v=3.3v FIGURE 10. GENERATING NEGATIVE SUPPLY FROM +5V
10 Component Value Selection Integrating Resistor Both the buffer amplifier and the integrator have a class A output stage with 100µA of quiescent current. They can supply 4µA of drive current with negligible nonlinearity. The integrating resistor should be large enough to remain in this very linear region over the input voltage range, but small enough that undue leakage requirements are not placed on the PC board. For 2V full scale, 470kΩ is near optimum and similarly a 47kΩ for a 200mV scale. Integrating Capacitor The integrating capacitor should be selected to give the maximum voltage swing that ensures tolerance buildup will not saturate the integrator swing (approximately. 0.3V from either supply). In the ICL7106 or the ICL7107, when the analog COMMON is used as a reference, a nominal +2V fullscale integrator swing is fine. For the ICL7107 with +5V supplies and analog COMMON tied to supply ground, a ±3.5V to +4V swing is nominal. For three readings/second (48kHz clock) nominal values for ClNT are 0.22µF and 0.10µF, respectively. Of course, if different oscillator frequencies are used, these values should be changed in inverse proportion to maintain the same output swing. An additional requirement of the integrating capacitor is that it must have a low dielectric absorption to prevent roll-over errors. While other types of capacitors are adequate for this application, polypropylene capacitors give undetectable errors at reasonable cost. Auto-Zero Capacitor The size of the auto-zero capacitor has some influence on the noise of the system. For 200mV full scale where noise is very important, a 0.47µF capacitor is recommended. On the 2V scale, a 0.047µF capacitor increases the speed of recovery from overload and is adequate for noise on this scale. Reference Capacitor A 0.1µF capacitor gives good results in most applications. However, where a large common mode voltage exists (i.e., the REF LO pin is not at analog COMMON) and a 200mV scale is used, a larger value is required to prevent roll-over error. Generally 1µF will hold the roll-over error to 0.5 count in this instance. Oscillator Components For all ranges of frequency a 100kΩ resistor is recommended and the capacitor is selected from the equation: Reference Voltage The analog input required to generate full scale output (2000 counts) is: VlN = 2VREF. Thus, for the 200mV and 2V scale, VREF should equal 100mV and 1V, respectively. However, in many applications where the A/D is connected to a transducer, there will exist a scale factor other than unity between the input voltage and the digital reading. For instance, in a weighing system, the designer might like to have a full scale reading when the voltage from the transducer is 0.662V. Instead of dividing the input down to 200mV, the designer should use the input voltage directly and select VREF = 0.341V. Suitable values for integrating resistor and capacitor would be 1 20kΩ and 0.22µF. This makes the system slightly quieter and also avoids a divider network on the input. The ICL7107 with ±5V supplies can accept input signals up to ±4V. Another advantage of this system occurs when a digital reading of zero is desired for VIN ≠ 0. Temperature and weighing systems with a variable fare are examples. This offset reading can be conveniently generated by connecting the voltage transducer between IN HI and COMMON and the variable (or fixed) offset voltage between COMMON and IN LO. ICL7107 Power Supplies The ICL7107 is designed to work from ±5V supplies. However, if a negative supply is not available, it can be generated from the clock output with 2 diodes, 2 capacitors, and an inexpensive lC. Figure 10 shows this application. See ICL7660 data sheet for an alternative. In fact, in selected applications no negative supply is required. The conditions to use a single +5V supply are: 1. The input signal can be referenced to the center of the common mode range of the converter. 2. The signal is less than ±1.5V. 3. An external reference is used. f 0.45 RC = ----------- For 48kHz Clock (3 Readings/sec), C 100pF. = ICL7107 V+ OSC 1 V- OSC 2 OSC 3 GND V+ V- = 3.3V 0.047 µF 10 µF + - IN914 IN914 CD4009 FIGURE 10. GENERATING NEGATIVE SUPPLY FROM +5V ICL7106, ICL7107, ICL7106S, ICL7107S
