基本语法元件例化与层次设计 23VHDL层次化结构模型 2.32元件例化 2.元件例化语句—一用来引用元件的并行语句。 当一个实体引用一个元件时,使用元件例化语句。元件例化语句指定该实例元件对应的元 件模型,并且指定了元件模型端口与实体中信号的关联关系。 例如 architecture Parent body of Parent is component And2 port(ll, 12: Bit; Ol: out Bit) nd component; signal SI, 32, S3: Bit Child And2 port map(l=>SI, 12=>S2, O1=>S3) nd Parent-body 2.3VHDL层次化结构模型 2.3.2元件例化 一个实体的结构体中引用某些元件,称为元件例化( Component instantiation),用元件例化 语句表示。该元件称为实例元件或例化元件( Instance)。各元件例化语句的执行顺序与书写 顺序无关 1.元件声明一一声明要调用某种模型的元件。 要引用的元件必须预先声明,称为元件声明。元件声明通常放在该结构体的声明部分,也 可以放在一个程序包中。 xkIr:http://www.61ic.com.cn/article/hdl/vHdl/200508/121.htMl VHDL: Creating a Hierarchical Design This example describes how to create a hierarchical design using VHDL. The top-level design, called top. vhd, implements an instance of the function logic. vhd In the top. vhd file, a component for the logic function is declared inside the architecture in which it is instantiated. The Component Declaration defines the ports of the lower-level function. 1. top. vhd (Top-level file USE ieee std logic 1164.ALL;
基本语法 元件例化与层次设计 2.3 VHDL 层次化结构模型 2.3.2 元件例化 2. 元件例化语句──用来引用元件的并行语句。 当一个实体引用一个元件时，使用元件例化语句。元件例化语句指定该实例元件对应的元 件模型，并且指定了元件模型端口与实体中信号的关联关系。 例如： architecture Parent_body of Parent is component And2 port(I1, I2: Bit; O1: out Bit)； end component; signal Sl，32，S3: Bit; begin Child: And2 port map(I1=>S1，I2=>S2，O1＝>S3); end Parent-body; 2.3 VHDL 层次化结构模型 2.3.2 元件例化 一个实体的结构体中引用某些元件，称为元件例化(Component instantiation)，用元件例化 语句表示。该元件称为实例元件或例化元件（instance）。各元件例化语句的执行顺序与书写 顺序无关。 1. 元件声明——声明要调用某种模型的元件。 要引用的元件必须预先声明，称为元件声明。元件声明通常放在该结构体的声明部分，也 可以放在一个程序包中。 来源：http://www.61ic.com.cn/Article/HDL/VHDL/200508/121.html VHDL: Creating a Hierarchical Design This example describes how to create a hierarchical design using VHDL. The top-level design, called top.vhd, implements an instance of the function logic.vhd. In the top.vhd file, a component for the logic function is declared inside the architecture in which it is instantiated. The Component Declaration defines the ports of the lower-level function. ----------------------------------------------------------------------------- 1. top.vhd (Top-level file) LIBRARY ieee; USE ieee.std_logic_1164.ALL;
ENTITY top Is PORT(w in, x in,y in IN std logic; IN std logic; z out OUT std logic) END top ARCHITECTURE a OF top Is COMPONENT logic PORT(a,b, c IN std logic; OUT std logic); END COMPONENT SIGNAL w reg, x reg, y_ reg, z reg std logic; BEGIN low logic: logic PORT MAP(a=wreg,b=>xreg,c→yreg,x→zreg), PROCESS(clock) BEGIN IF(clock'event AND clock='1)THEN w reg<=w In X reg<=x In END IF. END PROCESS a USE ieee std logic 1 164.ALL ENTITY logic IS PORT(a, b, c IN std logic, UT std logic) END logic ARCHITECTURE a OF logic IS BEGIN PROCESS (a,b, c)
ENTITY top IS PORT(w_in, x_in, y_in :IN std_logic; clock :IN std_logic; z_out :OUT std_logic); END top; ARCHITECTURE a OF top IS COMPONENT logic PORT(a,b,c :IN std_logic; x :OUT std_logic); END COMPONENT; SIGNAL w_reg, x_reg, y_reg, z_reg :std_logic; BEGIN low_logic : logic PORT MAP (a => w_reg, b => x_reg, c => y_reg, x => z_reg); PROCESS(clock) BEGIN IF (clock'event AND clock='1') THEN w_reg<=w_in; x_reg<=x_in; y_reg<=y_in; z_out<=z_reg; END IF; END PROCESS; END a; -------------------------------------------------------------------------------- 2. logic.vhd LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY logic IS PORT(a,b,c : IN std_logic; x : OUT std_logic); END logic; ARCHITECTURE a OF logic IS BEGIN PROCESS (a,b,c)
BEGIN <=(a and b)or c: END PROCESS END:
BEGIN x<=(a and b) or c; END PROCESS; END;