合肥工业大学：《EDA技术与应用》精品课程教学资源（文献资料）SDR SDRAM Controller White Paper

A吉RA White Paper SDR SDRAM Controller Introduction The single data rate(SDR)synchronous dynamic random access memory(SDRAM) controller provides a simplified interface to industry standard SDR SDRAM. The SDR SDRAM Controller is available in either Verilog HDL or VHDL and is optimized for the Altera APEX architecture. The SDR SDRAM Controller supports the following features. Burst lengths of 1, 2, 4, or 8 data words CAS latency of 2 or 3 clock cycles 16-bit programmable refresh counter used for automatic refresh 2-chip selects for SDRAM devices Supports the NoP, reada, WRItEA, AUTo_REFRESH, PRECHARGE, ACTIVATE, BURST_STOP, and LOAd MR commands Support for full-page mode operation Data mask line fo PLL to increase system performance Support for data-path widths of 16, 32, and 64 bits Figure I shows a system-level diagram of the SDR SDRAM Controller. Figure 1. SDR SDRAM Controller System-Level Diagram CMD[1: 0 DATAIN SDRAM Overview SDRAM is high-speed dynamic random access memory(DRAM) with a synchronous interface. The synchronous interface and fully-pipelined internal architecture of SDRAM allows extremely fast data rates if used efficiently Internally, SDRAM devices are organized in banks of memory, which are addressed by row and column. The number of row-and column-address bits and the number of banks depends on the size of the memory. August 2002, ver. 1.1

® White Paper SDR SDRAM Controller August 2002, ver. 1.1 1 M-WP-SDR-1.1 Introduction The single data rate (SDR) synchronous dynamic random access memory (SDRAM) controller provides a simplified interface to industry standard SDR SDRAM. The SDR SDRAM Controller is available in either Verilog HDL or VHDL and is optimized for the Altera® APEX™ architecture. The SDR SDRAM Controller supports the following features: ■ Burst lengths of 1, 2, 4, or 8 data words ■ CAS latency of 2 or 3 clock cycles ■ 16-bit programmable refresh counter used for automatic refresh ■ 2-chip selects for SDRAM devices ■ Supports the NOP, READA, WRITEA, AUTO_REFRESH, PRECHARGE, ACTIVATE, BURST_STOP, and LOAD_MR commands ■ Support for full-page mode operation ■ Data mask line for write operations ■ PLL to increase system performance ■ Support for data-path widths of 16, 32, and 64 bits Figure 1 shows a system-level diagram of the SDR SDRAM Controller. Figure 1. SDR SDRAM Controller System-Level Diagram SDRAM Overview SDRAM is high-speed dynamic random access memory (DRAM) with a synchronous interface. The synchronous interface and fully-pipelined internal architecture of SDRAM allows extremely fast data rates if used efficiently. Internally, SDRAM devices are organized in banks of memory, which are addressed by row and column. The number of row- and column-address bits and the number of banks depends on the size of the memory. SDR SDRAM Controller SDR SDRAM CLK SA CS_N BA CKE DQ CAS_N WE_N DQM RAS_N CLK CMD[1:0] CMDACK ADDR DATAIN DM DATAOUT

Altera Corporation SDR SDRAM Controller White Paper SDRAM is controlled by bus commands that are formed using combinations of the RASN, CASN, and WEN signals. For instance, on a clock cycle where all three signals are high, the associated command is a no operation(NOP).A NOP is also indicated when the chip select is not asserted. Table I shows the standard sDRaM bus commands. Table 1. sDRAM Bus commands Command Abbreviation RASN CASN WEN H ACT Burst terminate BT SDRAM banks must be opened before a range of addresses can be written to or read from. The row and bank to be opened are registered coincident with the ACT command. When a bank is accessed for a read or a write it may be necessary to close the bank and re-open it if the row to be accessed is different than the row that is currently opened Closing a bank is done with the PCh command The primary commands used to access SDRAM are RD and WR. when the WR command is issued, the initial col umn address and data word is registered. When a RD command is issued, the initial address is registered. The initial data appears on the data bus 1 to 3 clock cycles later. This is known as CAs latency and is due to the time required to physically read the internal DRAM core and register the data on the bus. The CAs latency depends on the speed the SDRAM and the frequency of the memory clock. In general, the faster the clock, the more cycles of CAs latency are required. After the initial RD or WR command, sequential read and writes continue until the burst length is eached or a BT command is issued. SDRAM memory devices support burst lengths of 1, 2, 4, or 8 data cycles. The ARF is issued periodically to ensure data retention. This function is performed by the SDR SDRAM Controller and is transparent to the user. The LMR is used to configure the SDRAM mode register which stores the CAs latency, burst length, burst type, and write burst mode. Consult the SDRAM specification for additional details. SDRAM comes in dual in-line memory modules(DIMMs), small-outline DIMMs(SO-DIMMs)and chips. To reduce SDRAM row and column addresses are multiplexed on the same pins. SDRAM often includes more than one bank of memory internally and DIMms may require multiple chip selects 2

Altera Corporation SDR SDRAM Controller White Paper 2 SDRAM is controlled by bus commands that are formed using combinations of the RASN, CASN, and WEN signals. For instance, on a clock cycle where all three signals are high, the associated command is a no operation (NOP). A NOP is also indicated when the chip select is not asserted. Table 1 shows the standard SDRAM bus commands. SDRAM banks must be opened before a range of addresses can be written to or read from. The row and bank to be opened are registered coincident with the ACT command. When a bank is accessed for a read or a write it may be necessary to close the bank and re-open it if the row to be accessed is different than the row that is currently opened. Closing a bank is done with the PCH command. The primary commands used to access SDRAM are RD and WR. When the WR command is issued, the initial col￾umn address and data word is registered. When a RD command is issued, the initial address is registered. The initial data appears on the data bus 1 to 3 clock cycles later. This is known as CAS latency and is due to the time required to physically read the internal DRAM core and register the data on the bus. The CAS latency depends on the speed of the SDRAM and the frequency of the memory clock. In general, the faster the clock, the more cycles of CAS latency are required. After the initial RD or WR command, sequential read and writes continue until the burst length is reached or a BT command is issued. SDRAM memory devices support burst lengths of 1, 2, 4, or 8 data cycles. The ARF is issued periodically to ensure data retention. This function is performed by the SDR SDRAM Controller and is transparent to the user. The LMR is used to configure the SDRAM mode register. which stores the CAS latency, burst length, burst type, and write burst mode. Consult the SDRAM specification for additional details. SDRAM comes in dual in-line memory modules (DIMMs), small-outline DIMMs (SO-DIMMs) and chips. To reduce pin count SDRAM row and column addresses are multiplexed on the same pins. SDRAM often includes more than one bank of memory internally and DIMMS may require multiple chip selects. Table 1. SDRAM Bus Commands Command Abbreviation RASN CASN WEN No operation NOP H H H Active ACT L H H Read RD H L H Write WR H L L Burst terminate BT H H L Precharge PCH L H L Autorefresh ARF L L H Load mode register LMR L L L

Altera Corporation SDR SDRAM Controller White Paper Functional Description Table 2 shows the SDR SDRAM Controller interface signals. All signals are synchronous to the system clock and outputs are registered at the SDR SDRAM Controller's outputs Table 2 Interface Signals Sig Name Active vO Description NA input System clock. RESET N ADDR [ASIZE-1: 01 emory address Input Memory address for read/write requests Width is set by CMD[2: 0] put Command request. MDACK Output Acknowledgment of the requested command DATAIN[DSIZE-1: 0]Input data put Input data bus width is set by DSIZE DATAOUT IDSIZE-1: 01 output data INA Output output data bus Width is set by size DM[(DSIZE/8)-1: 0] Data mask High input Masks individual bytes during data write SA[11:0 Address bus Output sA[l1: 0] are sampled during the ACT command to latch SA[n: 0] are sampled during the RD/WR mmand to latch the column address where n depends on he size of SDRAM used. SA[10] is sampled during the arged or the bank selected by BA[1 puts also provide the op-code during the LMR command BA[1:0] Bank address NA OUtput These signals determine to which bank the ACT,RD,WR,or cs_N[1:0 ut sDRAM chip selects Clock enable High Output SDRAM CKE input. AS N s strobe Low Output SDRAI nn address strobe Low output SDRAM command input. N Write enable Output SDRAM command input DQ[DSIZE-1: 0 DQM[(DSIZE/8)-1: 0]Data mask High Output SDRAM data masks, mask individual bytes during data

Altera Corporation SDR SDRAM Controller White Paper 3 Functional Description Table 2 shows the SDR SDRAM Controller interface signals. All signals are synchronous to the system clock and outputs are registered at the SDR SDRAM Controller’s outputs. Table 2. Interface Signals Signal Name Active I/O Description CLK Clock NA Input System clock. RESET_N Reset Low Input System reset. ADDR[ASIZE-1:0] Memory address NA Input Memory address for read/write requests. Width is set by ASIZE. CMD[2:0] Command NA Input Command request. CMDACK Command acknowledge High Output Acknowledgment of the requested command. DATAIN[DSIZE-1:0] Input data NA Input Input data bus. Width is set by DSIZE. DATAOUT[DSIZE-1:0] Output data NA Output Output data bus. Width is set by DSIZE. DM[(DSIZE/8)-1:0] Data mask High Input Masks individual bytes during data write SA[11:0] Address bus NA Output SA[11:0] are sampled during the ACT command to latch the row address. SA[n:0] are sampled during the RD/WR command to latch the column address where n depends on the size of SDRAM used. SA[10] is sampled during the PCH command to determine if all banks are to be pre￾charged or the bank selected by BA[1:0]. The address out￾puts also provide the op-code during the LMR command. BA[1:0] Bank address NA Output These signals determine to which bank the ACT, RD, WR, or PCH command is applied. CS_N[1:0] Chip selects Low Output SDRAM chip selects. CKE Clock enable High Output SDRAM CKE input. RAS_N Row address strobe Low Output SDRAM command input. CAS_N Column address strobe Low Output SDRAM command input. WE_N Write enable Low Output SDRAM command input. DQ[DSIZE-1:0] Data bus NA I/O SDRAM data bus. DQM[(DSIZE/8)-1:0] Data mask High Output SDRAM data masks, mask individual bytes during data write

Altera Corporation SDR SDRAM Controller White Paper SDRAM Controller Command interface The SDR SDRAM Controller provides a synchronous command interface to the SDRAM and several control reg ters. Table 3 shows the commands, which are described in following sections. The following rules apply to the com- All commands, except NOP, are driven by the user onto CMD(2: 0]: ADDR and datAin are set appropri ately for the requested command. The controller registers the command on the next rising clock edge To acknowledge the command the controller asserts CMDACK for one clock period or reada or WRitea commands the user should start receiving or writing data on dataout and DATAIN The user must drive NOP onto CMD [2: 0 by the next rising clock edge after CMDACK is asserted Table 3. Interface Commands Command Value Description NOP 000bNo operation 01b SDRAM read with auto precharge. 010b SDRAM write with auto precharge DRAM auto refresh. RECHARGE LOAD MODI 101b SDRAM load mode registe 110b Load controller configuration register. Load controller refresh p NOP Command NOP is a no operation command to the controller. When NOP is detected by the controller, it performs a NOP in the following clock cycle. A NOP must be issued the following clock cycle after the controller has acknowledged a com- mand. The NOP command has no affect on SDRAM accesses that are already in progress READA Command The READA command instructs the SDR SDRAM Controller to perform a burst read with auto-precharge to the SDRAM at the memory address specified by ADDR. The SDR SDRAM Controller issues an ACTIVATE command to the SDRAM followed by a READA command. The read burst data first appears on DATAOUT (RCD+CL 2) after the SDR SDRAM Controller asserts CMDACK During a REAda command the user must keep DM low.When he controller is configured for full-page mode, the READA command becomes READ (READ without auto-pre- charge). Figure 2 shows an example timing diagram for a READA command. The following sequence describes the general operation of the READA command: The user asserts REAdA. addr and dm The SDR SDRAM Controller asserts CMDACK to acknowledge the command and simultaneously starts issu- ing commands to the sdram devices One clock after CMDACK is asserted. the user must assert NOP The CMDACK presents the first read burst value on DATAOUT, the remainder of the read bursts follow every clock cycle

Altera Corporation SDR SDRAM Controller White Paper 4 SDRAM Controller Command Interface The SDR SDRAM Controller provides a synchronous command interface to the SDRAM and several control regis￾ters. Table 3 shows the commands, which are described in following sections. The following rules apply to the com￾mands: ■ All commands, except NOP, are driven by the user onto CMD[2:0]; ADDR and DATAIN are set appropri￾ately for the requested command. The controller registers the command on the next rising clock edge ■ To acknowledge the command the controller asserts CMDACK for one clock period ■ For READA or WRITEA commands, the user should start receiving or writing data on DATAOUT and DATAIN ■ The user must drive NOP onto CMD[2:0]by the next rising clock edge after CMDACK is asserted NOP Command NOP is a no operation command to the controller. When NOP is detected by the controller, it performs a NOP in the following clock cycle. A NOP must be issued the following clock cycle after the controller has acknowledged a com￾mand. The NOP command has no affect on SDRAM accesses that are already in progress. READA Command The READA command instructs the SDR SDRAM Controller to perform a burst read with auto-precharge to the SDRAM at the memory address specified by ADDR. The SDR SDRAM Controller issues an ACTIVATE command to the SDRAM followed by a READA command. The read burst data first appears on DATAOUT (RCD + CL + 2) after the SDR SDRAM Controller asserts CMDACK. During a READA command the user must keep DM low. When the controller is configured for full-page mode, the READA command becomes READ (READ without auto-pre￾charge). Figure 2 shows an example timing diagram for a READA command. The following sequence describes the general operation of the READA command: ■ The user asserts READA, ADDR and DM ■ The SDR SDRAM Controller asserts CMDACK to acknowledge the command and simultaneously starts issu￾ing commands to the SDRAM devices ■ One clock after CMDACK is asserted, the user must assert NOP ■ The CMDACK presents the first read burst value on DATAOUT, the remainder of the read bursts follow every clock cycle Table 3. Interface Commands Command Value Description NOP 000b No operation. READA 001b SDRAM read with auto precharge. WRITEA 010b SDRAM write with auto precharge. REFRESH 011b SDRAM auto refresh. PRECHARGE 100b SDRAM precharge all banks. LOAD_MODE 101b SDRAM load mode register. LOAD_REG1 110b Load controller configuration register. LOAD_REG2 111b Load controller refresh period register

Altera Corporation SDR SDRAM Controller White Paper Figure 2. READA Timing Diagram CMD X NoP X PRECHARGE NpP I CMDACK X1X2-XnX n-4Xn4Xn-dX n4X nix n CAS N 1X2X3x4aXn-4Xn-4X n D.C.=Dont Care WRITEA Command SDRAM at the memory address specified by ADDR. The SDR SDRAM Controller will issue an ACTIVaTE com- mand to the SDRAM followed by a WRITEA command. The first data value in the burst sequence must be presented with the Writea and addr address the host must start clocking data along with the desired dm values into the SDR SDRAM Controller(tRCD-2) clocks after the SDR SDRAM Controller has acknowledged the WRITEA com- mand See a sdram data sheet for how to use the data mask lines DM/DQM. When the SDR SDRAM Controller is in the full-page mode WRItEa becomes WRITE (write without auto-pre- charge). Figure 3 shows an example timing diagram for a WRITEA command. The following sequence describes the general operation of a WRITEA command: The user asserts WRITEA, ADDR, the first write data value on DATAIN, and the desired data mask value on The SDR SDRAM Controller asserts CMDACK to acknowledge the command and simultaneously starts issu- ing commands to the SDRAM devices One clock after CMDACK was asserted. the user asserts NoP on CMD The user clocks data and data mask values into the Sdr SdRAM Controller through datAin and dm

Altera Corporation SDR SDRAM Controller White Paper 5 Figure 2. READA Timing Diagram WRITEA Command The WRITEA command instructs the SDR SDRAM Controller to perform a burst write with auto-precharge to the SDRAM at the memory address specified by ADDR. The SDR SDRAM Controller will issue an ACTIVATE com￾mand to the SDRAM followed by a WRITEA command. The first data value in the burst sequence must be presented with the WRITEA and ADDR address. The host must start clocking data along with the desired DM values into the SDR SDRAM Controller (tRCD – 2) clocks after the SDR SDRAM Controller has acknowledged the WRITEA com￾mand. See a SDRAM data sheet for how to use the data mask lines DM/DQM. When the SDR SDRAM Controller is in the full-page mode WRITEA becomes WRITE (write without auto-pre￾charge). Figure 3 shows an example timing diagram for a WRITEA command. The following sequence describes the general operation of a WRITEA command: ■ The user asserts WRITEA, ADDR, the first write data value on DATAIN, and the desired data mask value on DM ■ The SDR SDRAM Controller asserts CMDACK to acknowledge the command and simultaneously starts issu￾ing commands to the SDRAM devices ■ One clock after CMDACK was asserted, the user asserts NOP on CMD ■ The user clocks data and data mask values into the SDR SDRAM Controller through DATAIN and DM Address 1 2 3 4 ... n-6 n-5 n-4 Row Column CLK CMD CMDACK ADDR DATAOUT DQM RAS_N CAS_N WE_N DQ SA BA CS_N CKE READA NOP 1 2 ... n-8 n-7 n-6 n-5 n-4 NOP D.C. D.C. = Don't Care D.C. PRECHARGE NOP n-3 n-2 n-1 n n-3 n-2 n-1 n

Altera Corporation SDR SDRAM Controller White Paper Figure 3. WRITEA Timing Diagram CKE WRJTEA X NOP CMDACK DATAINDc I IX 5x6x7x ax p.c. Ⅸ X XXX p.c. RAS N CAS N DOM Ⅸ XXXX D.C.= Don't Care REFRESH Command The REFRESH command instructs the SDR SDRAM Controller to perform an ARF command to the SDram. The SDR SDRAM Controller acknowledges the REFRESH command with CMDACK. Figure 4 shows an example timing diagram of the REFRESH command. The following sequence describes the general operation of a REFRESH com- mand The SDR SDRAM Controller asserts CMDACK to acknowledge the command and simultaneously starts issu- ing commands to the sdram devices The user asserts NoP on CMD

Altera Corporation SDR SDRAM Controller White Paper 6 Figure 3. WRITEA Timing Diagram REFRESH Command The REFRESH command instructs the SDR SDRAM Controller to perform an ARF command to the SDRAM. The SDR SDRAM Controller acknowledges the REFRESH command with CMDACK. Figure 4 shows an example timing diagram of the REFRESH command. The following sequence describes the general operation of a REFRESH com￾mand: ■ The user asserts REFRESH on the CMD input ■ The SDR SDRAM Controller asserts CMDACK to acknowledge the command and simultaneously starts issu￾ing commands to the SDRAM devices ■ The user asserts NOP on CMD Address 1234567 Row Column CLK CMD CMDACK ADDR DATAIN DQM RAS_N CAS_N WE_N DQ SA BA CS_N CKE WRITEA NOP 1 2345678 DM D.C. = Don't Care NOP D.C. D.C. D.C. D.C. D.C. D.C. 8

Altera Corporation SDR SDRAM Controller White Paper Figure 4. REFRESH Timing Diagram CMD EFRESH CMDACK RAS N CAS N PRECHARGE Command The PRECHARGE command instructs the SDR SDRAM Controller to perform a PCH command to the SDram The SDR SDRAM Controller acknowledges the command with CMDACK. The PCH command is also used to gener ate a burst stop to the SDRAM. Using PRECHARGe to terminate a burst is only supported in the full-page mode Note that the SDR SDRAM Controller adds a latency from when the host issues a command to when the SDraM sees the PRECHaRGE command of 4 clocks. If a full-page read burst is to be stopped after 100 cycles, the PRE- CHARGE command must be asserted (4+Cl-1)clocks before the desired end of the burst(CL-I requirement imposed by the SDRaM devices). So if the CAs latency is 3, the PRECHARGE command must be issued (100-3 1-4)=92 clocks into the burst Figure 5 shows an example timing diagram of the PRECHARGE command. The following sequence describes the general operation of a PRECHARGE command The user asserts PRECharGe on CMI The SDR SDRAM Controller asserts CMDACK to acknowledge the command and simultaneously starts issu- ing commands to the sdram devices The user asserts NoP on CMD

Altera Corporation SDR SDRAM Controller White Paper 7 Figure 4. REFRESH Timing Diagram PRECHARGE Command The PRECHARGE command instructs the SDR SDRAM Controller to perform a PCH command to the SDRAM. The SDR SDRAM Controller acknowledges the command with CMDACK. The PCH command is also used to gener￾ate a burst stop to the SDRAM. Using PRECHARGE to terminate a burst is only supported in the full-page mode. Note that the SDR SDRAM Controller adds a latency from when the host issues a command to when the SDRAM sees the PRECHARGE command of 4 clocks. If a full-page read burst is to be stopped after 100 cycles, the PRE￾CHARGE command must be asserted (4 + CL – 1) clocks before the desired end of the burst (CL – 1 requirement is imposed by the SDRAM devices). So if the CAS latency is 3, the PRECHARGE command must be issued (100 – 3 – 1 – 4) = 92 clocks into the burst. Figure 5 shows an example timing diagram of the PRECHARGE command. The following sequence describes the general operation of a PRECHARGE command: ■ The user asserts PRECHARGE on CMD ■ The SDR SDRAM Controller asserts CMDACK to acknowledge the command and simultaneously starts issu￾ing commands to the SDRAM devices ■ The user asserts NOP on CMD CLK CMD CMDACK DQM RAS_N CAS_N WE_N DQ SA BA CS_N CKE REFRESH NOP CLK FREQ = 133 MHz NOP

Altera Corporation SDR SDRAM Controller White Paper Figure 5. PRECHARGE Timing Diagram MD NOP XPREFHAF CAS N WE_N DOM LOAD MODE Command The LOAD_MODE command instructs the SDR SDRAM Controller to perform a LMr command to the SDRAM The value that is to be written into the SDRAM mode register must be present on ADDR [11: 0] with the LOAD_MODE command. The value on ADDR[11: 0] is mapped directly to the SDRAM pins All-A0 when the SDR SDRAM Controller issues the LMR to the SDRAM. Figure 6 shows an example timing diagram. The following sequence describes the general operation of a LOAD_MODE command The users asserts LOAD MODE on CMD The SDR SDRAM Controller asserts CMDACK to acknowledge the command and simultaneously starts issu- ing commands to the sdram devices One clock after the SDR SDRAM Controller asserts CmDACK, the users asserts NoP on CMD

Altera Corporation SDR SDRAM Controller White Paper 8 Figure 5. PRECHARGE Timing Diagram LOAD_MODE Command The LOAD_MODE command instructs the SDR SDRAM Controller to perform a LMR command to the SDRAM. The value that is to be written into the SDRAM mode register must be present on ADDR[11:0] with the LOAD_MODE command. The value on ADDR[11:0] is mapped directly to the SDRAM pins A11-A0 when the SDR SDRAM Controller issues the LMR to the SDRAM. Figure 6 shows an example timing diagram. The following sequence describes the general operation of a LOAD_MODE command: ■ The users asserts LOAD_MODE on CMD ■ The SDR SDRAM Controller asserts CMDACK to acknowledge the command and simultaneously starts issu￾ing commands to the SDRAM devices ■ One clock after the SDR SDRAM Controller asserts CMDACK, the users asserts NOP on CMD CLK CMD CMDACK DQM RAS_N CAS_N WE_N DQ SA BA CS_N CKE PRECHARGE NOP CLK FREQ = 133 MHz NOP

Altera Corporation SDR SDRAM Controller White Paper Figure 6. LOAD_MODE Timing Diagram CMD RAS N DOM LOAD REGI Command The load regi command instructs the SDR SDRAM Controller to load the internal configuration register REGI The value that is to be written into REGI must be presented on the ADDR input simultaneously with the assertion of he command LOAD_REGl. Table 4 shows the bit assignments for rEGI Table 4. REG1 Bit Definitions Label ADDR Bits Description [1: 0] CAS latency setting. RCD [3: 2]RAS to CaS delay in number of clocks. REFRESH command duration in clocks DR SDRAM Controller mode, 0=normal 1=page mode. [12: 9]Burst length, valid values are 1,2,4,8. CL is the CAs latency of the SDRAM memory in clock periods and is dependent on the memory device speed grade and clock frequency. Consult the SDRAM data sheet for appropriate settings. CL must be set to the same value as CL for the SDRAM memory devices. RCD is the ras to cas delay in clock periods and is dependent on the SDRAM speed grade and clock frequency RCD=inT(RoD/clock_period), where tRCD is the value from the SdraM data sheet and clock_period is the clock period of the SDR SDRAM Controller and SDRAM clock

Altera Corporation SDR SDRAM Controller White Paper 9 Figure 6. LOAD_MODE Timing Diagram LOAD_REG1 Command The LOAD_REG1 command instructs the SDR SDRAM Controller to load the internal configuration register REG1. The value that is to be written into REG1 must be presented on the ADDR input simultaneously with the assertion of the command LOAD_REG1. Table 4 shows the bit assignments for REG1. CL is the CAS latency of the SDRAM memory in clock periods and is dependent on the memory device speed grade and clock frequency. Consult the SDRAM data sheet for appropriate settings. CL must be set to the same value as CL for the SDRAM memory devices. RCD is the RAS to CAS delay in clock periods and is dependent on the SDRAM speed grade and clock frequency. RCD = INT(tRCD/clock_period), where tRCD is the value from the SDRAM data sheet and clock_period is the clock period of the SDR SDRAM Controller and SDRAM clock. Table 4. REG1 Bit Definitions Label ADDR Bits Description CL [1:0] CAS latency setting. RCD [3:2] RAS to CAS delay in number of clocks. RRD [7:4] REFRESH command duration in clocks. PM [8] SDR SDRAM Controller mode, 0 = normal 1 = page mode. BL [12:9] Burst length, valid values are 1, 2, 4, 8. CLK CMD CMDACK DQM RAS_N CAS_N WE_N DQ SA BA CS_N ADDR LOAD_MODE NOP CLK FREQ = 133 MHz NOP MODE VALUE

Altera Corporation SDR SDRAM Controller White Paper RRD is the refresh to rAs delay in clock periods. RRD is dependent on the SDRAM speed grade and clock fre- RRD=INT(IRRD/clock_period), where tRRD is the value from the SDram data sheet and clock_period is the clock period of the SDR SDRAM controller and SDRAM clock. PM is the page mode bit. If PM=0, the SDR SDRAM Controller operates in non-page mode If PM=l, the SDr SDRAM Controller operates in page-mode. See Section "Full-Page Mode Operation"on page 14 for more informa- BL is the burst length the sdram devices have been configured for LOAD REG2 Command The LOAD_ REG2 command instructs the SDR SDRAM Controller to load the internal configuration register REG2 REG2 is a 16-bit value that represents the period between REFRESH commands that the SDR SDRAM Controller issues. The value is set by the equation int(refresh_periodclock_period) For example, if a SDRAM device connected to the SDR SDRAM Controller has a 64-ms, 4096-cycle refresh require nent the device must have a rEFrESH command issued to it at least every 64ms/4096=15.62509μs If the SDRAM and SDR SDRAM Controller are clocked by a 100 MHz clock, the maximum value of REG2 is 15.625 Hs/0.01 Hs=1562d. The value that is to be written into REG2 must be presented on the ADDR input simulta- neously with the assertion of the command LOAD_REG2 SDRAM Device Initialization and SDR SdraM Controller Configuration The SdraM devices that are connected to the SDR SDRAM Controller must be initialized before they can be accessed. This initialization process sets the burst length, CAS latency, burst type, and operation mode for the SDRAM devices. After the sdram devices are initialized the Sdr sdraM Controller's configuration registers must be set To initialize the SDram devices and the SDR SDRAM Controller, perform the following steps CHARGE Assert a LOAD_MODE command(see "LOAD_MODE Command"on page 8) Assert a LOAD_REG2 command(see"LOAD_REG2 Command"on page 10 Assert a LOAD_REGI command(see""LOAD_REGI Command"on page 9) Architecture The SDR SDRAM Controller consists of four main modules: the sdram controller, control interface, command, and data path modules. The SDRAM controller module is the top-level module that instantiates the three lower mod- ules and brings the whole design together. The control interface module accepts commands and related memory addresses from the host, decoding the command and passing the request to the command module. The command module accepts commands and addresses from the control interface module, and generates the proper commands to the SDRAM. The data path module handles the data path operations during WRITEA and READA commands. The SDRAM controller module also instantiates a PlL that is used in the CLOCK_ LOCK mode to improve 1O timing. This PLL is not essential to the operation of the SDR SDRAM Controller and can be easily removed. Figure 7 shows the SDR SDRAM Controller block diagram

Altera Corporation SDR SDRAM Controller White Paper 10 RRD is the refresh to RAS delay in clock periods. RRD is dependent on the SDRAM speed grade and clock fre￾quency. RRD= INT(tRRD/clock_period), where tRRD is the value from the SDRAM data sheet and clock_period is the clock period of the SDR SDRAM controller and SDRAM clock. PM is the page mode bit. If PM = 0, the SDR SDRAM Controller operates in non-page mode. If PM = 1, the SDR SDRAM Controller operates in page-mode. See Section “Full-Page Mode Operation” on page 14 for more informa￾tion. BL is the burst length the SDRAM devices have been configured for. LOAD_REG2 Command The LOAD_REG2 command instructs the SDR SDRAM Controller to load the internal configuration register REG2. REG2 is a 16-bit value that represents the period between REFRESH commands that the SDR SDRAM Controller issues. The value is set by the equation int(refresh_period/clock_period). For example, if a SDRAM device connected to the SDR SDRAM Controller has a 64-ms, 4096-cycle refresh require￾ment the device must have a REFRESH command issued to it at least every 64 ms/4096 = 15.625 09 µs. If the SDRAM and SDR SDRAM Controller are clocked by a 100 MHz clock, the maximum value of REG2 is 15.625 µs/0.01 µs = 1562d. The value that is to be written into REG2 must be presented on the ADDR input simulta￾neously with the assertion of the command LOAD_REG2. SDRAM Device Initialization and SDR SDRAM Controller Configuration The SDRAM devices that are connected to the SDR SDRAM Controller must be initialized before they can be accessed. This initialization process sets the burst length, CAS latency, burst type, and operation mode for the SDRAM devices. After the SDRAM devices are initialized, the SDR SDRAM Controller’s configuration registers must be set. To initialize the SDRAM devices and the SDR SDRAM Controller, perform the following steps: ■ Assert the PRECHARGE command (see “PRECHARGE Command” on page 7) ■ Assert a LOAD_MODE command (see “LOAD_MODE Command” on page 8) ■ Assert a LOAD_REG2 command (see “LOAD_REG2 Command” on page 10) ■ Assert a LOAD_REG1 command (see “LOAD_REG1 Command” on page 9) Architecture The SDR SDRAM Controller consists of four main modules: the SDRAM controller, control interface, command, and data path modules. The SDRAM controller module is the top-level module that instantiates the three lower mod￾ules and brings the whole design together. The control interface module accepts commands and related memory addresses from the host, decoding the command and passing the request to the command module. The command module accepts commands and addresses from the control interface module, and generates the proper commands to the SDRAM. The data path module handles the data path operations during WRITEA and READA commands. The SDRAM controller module also instantiates a PLL that is used in the CLOCK_LOCK mode to improve I/O timing. This PLL is not essential to the operation of the SDR SDRAM Controller and can be easily removed. Figure 7 shows the SDR SDRAM Controller block diagram