第9章第2节 QuartusⅢ中的优化设计 配置、仿真和报告 课程讲义 合肥工业大学彭良清 上一章 下一章
第9章第2节 Quartus II中的优化设计 配置、仿真和报告 课程讲义 下一章 合肥工业大学 彭良清 上一章
本节内容 时序分析的基本概念和术语 Quartus‖中的时序约束设置 三. Quartus‖中的时序分析 四. Quartus川中的编译报告 五.FPGA恭片的时序指标举例 有关时序分析更多的资料请参见 http://www.altera.com/quartushelp/istjsp?keyw ord=verificationanalysis
本节内容 一． 时序分析的基本概念和术语 二． Quartus II中的时序约束设置 三． Quartus II中的时序分析 四． Quartus II中的编译报告 五． FPGA芯片的时序指标举例 有关时序分析更多的资料请参见 http://www.altera.com/quartushelp/list.jsp?keyw ord=verificationanalysis
时序分析的基本概念和术语 1.时钟建立时间(tsv: clock setup time) 2.时钟保持时间(tn, clock hold time) 3.时钟输出延时(tco: Clock to output delay 4.时钟偏斜( Clock skew) 5.引脚到引脚的延时(tpo:Pin- to-Pin Delay 6.时序裕量( Slack) 7.独立时钟和衍生时钟( Absolute clock& Derived clock 8.占空比( Duty Cycle) 9.行波时钟( Ripple Clock
时序分析的基本概念和术语 1. 时钟建立时间(tSU:clock setup time) 2. 时钟保持时间(th:clock hold time) 3. 时钟输出延时(tCO :Clock to output delay) 4. 时钟偏斜（ Clock Skew） 5. 引脚到引脚的延时(tPD: Pin-to-Pin Delay) 6. 时序裕量（Slack） 7. 独立时钟和衍生时钟（Absolute Clock & Derived Clock） 8. 占空比（Duty Cycle） 9. 行波时钟（Ripple Clock）
建立时间和保持时间 Inputs Combinatorial Output L。gic Clock Th D /: Clock
建立时间 和 保持时间
ts(clock setup trme)rE Th Data Delay D Micro tsu data SU一 clk Clock Delay tsu Data Delay Micro tsu- Clock Delay
tSU= Data Delay + Micro tSU - Clock Delay tSU (clock setup time)
Inputs Combinatorial tH(clock hold timb) ock Th Data Delay D Micro tH data H clk Clock Delay stH=Clock Delay + Micro tH- Data Delay
tH=Clock Delay + Micro tH - Data Delay tH (clock hold time)
tco(clock to output delay Micro tco C clk Data Delay Clock nela stco=Clock Delay+Micro Tco+Data Delay
tCO (Clock to output delay) tCO=Clock Delay+Micro Tco+Data Delay
时钟偏斜( clock skew):图示 Regl Reg2 3 ns delay〔 skew clk1 clk2 15 2 Setup Requirement 15 ns Hold Requirement=3 ns
时钟偏斜（clock skew）:图示
时钟偏斜( clock skew) e The difference in the arrival time of a clock signal at two different registers, o which can be caused by path length differences between two clock paths o or by using gated or rippled clocks Clock skew is the most common cause of internal hold violations, as shown in figure 1
时钟偏斜（clock skew） ❖ The difference in the arrival time of a clock signal at two different registers, ❖ which can be caused by path length differences between two clock paths, ❖ or by using gated or rippled clocks. ❖ Clock skew is the most common cause of internal hold violations, as shown in figure 1
引脚间延时tPD(pnto- pin delay) .o The time required for a signal from an input pin to propagate through combinational logic and appear at an external output pin 冷 In the Quartus‖ software, you can specify the required tPD for the entire project and/or for any cRinput pin, oUtput pin, cR bidirectional pin .o You can also assign a point-to-point tPD assignment to specify the required delay between R an input pin and a register, cR a register and a register, Ra register and an output pin
引脚间延时tPD (pin-to-pin delay) ❖ The time required for a signal from an input pin to propagate through combinational logic and appear at an external output pin. ❖ In the Quartus® II software, you can specify the required tPD for the entire project and/or for any input pin, output pin, bidirectional pin. ❖ You can also assign a point-to-point tPD assignment to specify the required delay between an input pin and a register, a register and a register, a register and an output pin