Instruction-Set Processor Design Architecture (ISA)programmer/compiler view -"functional appearance to its immediate user/system Application >"hello Software world!" programmer" Operating -Opcodes,addressing modes,architected registers Systems IEEE floating point Architecture -机器语言 Micro- architecture Implementation (JArch)processor designer view -"logical structure or organization that performs the architecture" Digital Circuits o -functional units,pipelining,caches,physical registers Analog Circuits Realization (chip)chip/system designer view Devices -"physical structure that embodies the implementation' -Gates,cells,transistors,wires Physics
Instruction-Set Processor Design • Architecture (ISA) programmer/compiler view – “functional appearance to its immediate user/system programmer” – Opcodes, addressing modes, architected registers, IEEE floating point – 机器语言 • Implementation (µArch) processor designer view – “logical structure or organization that performs the architecture” – functional units, pipelining, caches, physical registers • Realization (chip) chip/system designer view – “physical structure that embodies the implementation” – Gates, cells, transistors, wires
内容提要 ●（ CPU uArch实现概要 ·设计步骤 -4步法：数据通路，控制器，定时，综合 定时：指令周期，时钟周期，机器周期（总线周期，访存周期） 。 单周期设计：早期R1SC采用，$4.3，$4.4 -输入：RV32IISA -输出：功能部件，数据通路，控制器（真值表），Clocking ·性能分析 Digital Design and Computer Architecture SECONO EDTION COD5-RV - $4.1:引言 -$4.2:逻辑设计的一般方法（设计约定) M< -$4.3:数据通路 David M.Harris,Sarah L.Harris, $4.4:单周期实现(ALU控制，主控制器) Digital Design and Computer Architecture,2012
内容提要 • CPU uArch实现概要 • 设计步骤 – 4步法：数据通路，控制器，定时，综合 – 定时：指令周期，时钟周期，机器周期（总线周期，访存周期） • 单周期设计：早期RISC采用，$4.3，$4.4 – 输入：RV32I ISA – 输出：功能部件，数据通路，控制器（真值表），Clocking • 性能分析 • COD5-RV – $4.1：引言 – $4.2：逻辑设计的一般方法（设计约定） – $4.3：数据通路 – $4.4：单周期实现（ALU控制，主控制器） David M. Harris, Sarah L. Harris， Digital Design and Computer Architecture, 2012
微结构：数据通路，控制器 Control Signals 内存，I0 Control Arithmetic Internal Data& Unit Logic Unit data bus Addr Registers Instruction Input Op&BEN&mode Decoder 控制单元 数据通路 (执行单元) Control Signals Control Signals EPROM RAM Cs CS A9 A0-A8 A9 A0-A8 Address Bus n Data Bus m PROCESSOR RD WR
微结构：数据通路，控制器
ISA Processor Design:RV的核心子集 Example instruction Instruction name Meaning add x1,x2,x3 Add Regs[x1]-Regs[x2]+Regs[x3] addi x1,x2,3 Add immediate unsigned Regs[x1]-Regs[x2]+3 1wx1,60(x2) Load word Regs[x1]-64 Mem[60+Regs[x2]])32 Mem[60+Regs[x2]] swx3,500(x4) Store word Mem[500+Regs[x4]]-32Regs[x3]32.63 beq x3,x4,offset Branch equal zero if (Regs[x3]--Regs[x4])PC-PC+(offset<<1) jal xl,offset Jump and link Regs[x1]-PC+4;PC-PC+(offset<<1) jalr x1.x2,offset Jump and link register Regs[x1]-PC+4;PC+-Regs[x2]+offset Name Field Comments (Field size) 7 bits 5 bits 5 bits 3 bits 5 bits 7 bits R-type funct7 rs2 rs1 funct3 rd opcode Arithmetic instruction format I-type immediate[11:0] rs1 funct3 rd opcode Loads immediate arithmetic S-type immed[11:5] rs2 rs1 funct3 immed[4:0] opcode Stores SB-type immed[12.10:5] rs2 rs1 funct3 immed[4:1,11] opcode Conditional branch format UJ-type immediate20,10:1,11,19:12] rd opcode Unconditional jump format U-type immediate[31:12] rd opcode Upper immediate format
ISA Processor Design：RV的核心子集
数据通路Abstract/Simplified View RV Instruction Execution Phases Instruction Fetch Data Instruction Decode Regs威er# Address Instruction Registers Address Register Fetch Regster memory Data Register# memory ALU Operations Deta -Optional Memory Operations Optional Register Write back Calculate Next Instruction Address Two types of functional units elements that operate on data values (combinational) elements that contain state (sequential) 6
数据通路Abstract / Simplified View • RV Instruction Execution Phases – Instruction Fetch – Instruction Decode – Register Fetch – ALU Operations – Optional Memory Operations – Optional Register Write back – Calculate Next Instruction Address • Two types of functional units – elements that operate on data values (combinational) – elements that contain state (sequential) 6
Controller慨览：RV64/RV32附录C DATAPATH REGISTER MUX DFF din DFF din- addr- DFF DATA INSTRUC. -dout ALU -dout din- -dout -dout init- PC -addr addr- REGISTER -inst din- MEMORY din din- sel DFF wrPC clk ALUop rdM wrM clk wrlR clk wrR clk sel ALUop wrR rdM wrM wrPC wrlR opcode- Control clk- Unit 1.Instruction 2.Decode/ 3.Execute 4.Memory 5.R6g (FSM) Fetch Register Write Read 功能：译码，正确的时间产生正确的控制信号 Clk,Reset? 由两部分构成：计算输出信号和下一状态+时序控制 一组合逻辑（计算），顺序逻辑（状态保存，时序控制） -真值表，FSM(ROM,PLA,Sequencer),微程序
Controller概览：RV64/RV32附录C • 功能：译码，正确的时间产生正确的控制信号 – Clk，Reset？ • 由两部分构成：计算输出信号和下一状态 + 时序控制 – 组合逻辑（计算），顺序逻辑（状态保存，时序控制） – 真值表，FSM（ROM，PLA，Sequencer），微程序
PC,立即数生成/符号扩展，MUX,3-8译码器 M 32 Imm 64 B PC Gen Select 每个周期结束时写入npc 无需写控制信号（简化，图4-5） M 641 64 Outo Inputs Outputs Out1 12 11 10 Out7 Out6 Out5 Out4 Out3 Out2 Out1 Outo Out2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 Out3 Decoder 0 1 0 0 0 0 0 0 0 0 Out4 0 1 1 0 0 0 0 1 0 0 0 Out5 1 0 0 0 0 0 1 0 0 0 0 Out6 1 0 1 0 0 1 0 0 0 0 0 2 1 0 0 0 0 0 0 0 0 Out7 1 1 1 0 0 0 0 0 0 0
PC，立即数生成/符号扩展，MUX，3-8译码器 每个周期结束时写入npc 无需写控制信号（简化，图4-5）
$A.8.1:D触发器，寄存器 D Master Slave (Data) 0 Clock C C Clock D锁存器：ck电平控制 一位D触发器：ck边沿控制 Preset Preset 数据输入 数据输出 数据使能 D触发器 时钟 Clear 复位 带清零Clear和预置Preset的D触发器 一位寄存器，数据使能=write,clk
$A.8.1：D触发器，寄存器 D 锁存器：clk电平控制 一位 D 触发器：clk边沿控制 ＝ ＝ 带清零Clear和预置Preset的D 触发器 一位寄存器，数据使能=write，clk
n位RegFile:图A-8-7,A-8-8,A-8-9 Read register Write number 1 Register 0 0 Register 0 Register 1 1 M n-to-2n u Read data 1 Register number decoder Register n-2 n-1 Register 1 Register n- n Read register number 2 Register n-2 M u Read data 2 Register n-1 Register data Registers Read register 1 Read clk、Clear、Preset、write? Read data 1 register 2 读操作，写操作 Write Read register data 2 “两读一写”，“异步读，同步写” Write data Re gWrite
n位RegFile：图A-8-7，A-8-8，A-8-9 clk、Clear、Preset、write？ 读操作，写操作 “两读一写”， “异步读，同步写
RegFile读写操作约定：后写，先写 ·不同寄存器读写：在一个周期内，RF支持“两读一写” ·写控制RegWrite.与clk同步，边沿触发 o 同一寄存器读写：一个周期内同时对同一寄存器读和写 一条指令一个周期内读写同一寄存器：add$t0,$s2,$t0 ·后写(late write):前半周期读，后半周期写。一一单周期用！ -先读后写：一个周期内完成读写，但读出的是上一周期写入的值。图4-7 ·两条指令一个周期内读写同一寄存器： 结构冲突 ·先写(early write):前半周期写，后半周期读。一一流水线用！ -先写后读：读出的是前半周期末写入的值。图4-32，图4-50 Read Port 1 Registers Read Write register 1 Read Adr 1 Read data 1 Read register 2 Adr 1 Read Write Read Port 2 register data 2 Write data Write RegWrite Read 11 Adr 2
RegFile读写操作约定：后写，先写 • 不同寄存器读写：在一个周期内，RF支持“两读一写” • 写控制RegWrite与clk同步，边沿触发 • 同一寄存器读写：一个周期内同时对同一寄存器读和写 • 一条指令一个周期内读写同一寄存器： • 后写（late write）：前半周期读，后半周期写。——单周期用！ –先读后写：一个周期内完成读写，但读出的是上一周期写入的值。图4-7 • 两条指令一个周期内读写同一寄存器：结构冲突 • 先写（early write）：前半周期写，后半周期读。——流水线用！ –先写后读：读出的是前半周期末写入的值。图4-32，图4-50 11