答疑时间:周四下午2:30~5:30 地点:西主楼4区210室 习题1 2-1(a),2-2(b),2-3(c),2-6(c) 3-1,3-2(a),3-3(b),3-4(c),3-5(d),3-9(a) 请用VHDL语言描述与或非门和异或门
答疑时间：周四下午2：30～5：30 地点：西主楼4区210室 习题1 2-1(a), 2-2(b), 2-3(c), 2-6(c) 3-1,3-2(a), 3-3(b), 3-4(c), 3-5(d), 3-9(a) 请用VHDL语言描述与或非门和异或门
2-1(a)(12.062)10=(100001舍入误差<28 2-2(b)(10111.010)2=25+23+22+222+2<(A63125) 23()(6237)86×82+2×81+3×8+7×81+780 (403984375)10 =(11001001111238 =(110010012 =(000110010011111100216 =(193FC)16 26(c)(0011010001110001)210=(3471)10
2-1(a) (12.062)10=(1100.00001111)2 舍入误差<2-8 2-2(b)(101110.0101)2=25+23+22+21+2-2+2-4=(46.3125)10 2-3(c)(623.77)8=6×8 2+2×8 1+3×8 0+7×8 -1+7×8 -2 =（403.984375）10 =（110 010 011.111 111）2-8 =（110010011.111111）2 =（0001 1001 0011.1111 1100）2-16 =（193.FC）16 2-6(c)（0011 0100 0111 0001）2-10 =（3471）10
三个控制开关A,B,C,有动作为1,A 无动作为0,通道灯的状态Y有变B Y 化为1,无变化为0 C A B C A00 cY 001 B0011001 0 Y 111 01001 Y=ABC+ABC+ABC+ABC=ABoC 3-1能从三处分别独立进行控制的通道灯电路
3-1 能从三处分别独立进行控制的通道灯电路 A B Y C 三个控制开关A,B,C，有动作为1， 无动作为0，通道灯的状态Y有变 化为1，无变化为0 A B C Y 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 0 0 1 1 0 1 0 1 1 0 0 1 1 1 1 Y = ABC + ABC + ABC + ABC = A B C Y + _ A B C
3-2(a)求反函数,并化简 Y=(BC + AD(AB+CD) Y=(B+C)(A+D)+(A+B)(C+D) ab+bd+ ac +cd+ a- c+ ad+bc t bd =AB+Ac+bc+cd+ac +ad+bd+bd abC+ bc+Cd+Acd+bd+BD =A+BC+cd+a+bd+ bd =1+bC +cd+bd+Bd 1
3-2(a) 求反函数，并化简 1 1 ( )( ) ( )( ) ( )( ) = = + + + + = + + + + + = + + + + + = + + + + + + + = + + + + + + + = + + + + + = + + BC CD BD BD A BC CD A BD BD ABC BC CD ACD BD BD AB AC BC CD A C AD BD B D AB B D AC CD A C AD BC BD Y B C A D A B C D Y BC AD AB CD
3-3(b)写成最大项和最小项的形式 FW, X,Y,2=YZ+WXY+WXZ+w. X. Z (WX+WX+Wx+W·X)Y2+WYY(Z+2)+WX(Y+Y)Z+W·X·(Y+Y)z WXYZ+W.Z+WXYZ+W.X.YZ+WXY.2+WXY2+W.X.YZ =m13+m+ms+m1+m12+m14+m3 ∑m,i=1.39121314 =M,k=0.246,7:810115 (W+X+Y+ow+X+Y+ZO+X+Y+2) +X+Y+Zw+X+r+Zo+X+r+2) (W+X+r+Z +X+r+z)(w+X+r+2) 3-4(c)变换成另一种形式 F(￥,Y,Z)=∏M(O,3,6,7)=∑m(1,2,4
3-3(b) 写成最大项和最小项的形式 ( )( )( ) ( )( )( ) ( )( )( ) , 0,2,4,6,7,8,10,11,15 , 1,3,5,9,12,13,14 ( ) ( ) ( ) ( ) ( , , , ) 1 3 9 5 1 1 2 1 4 3 W X Y Z W X Y Z W X Y Z W X Y Z W X Y Z W X Y Z W X Y Z W X Y Z W X Y Z M k m i m m m m m m m WXYZ WX YZ WXYZ W X YZ WXY Z WXYZ W X YZ WX WX WX W X YZ WXY Z Z WX Y Y Z W X Y Y Z F W X Y Z YZ WXY WXZ W X Z k i + + + + + + + + + + + + + + + + + + = + + + + + + + + + = = = = = + + + + + + = + + + + + + = + + + + + + + + + = + + + 3-4(c) 变换成另一种形式 F(X,Y,Z) = M(0,3,6,7) = m(1,2,4,5)
3-5(d)卡诺图化简 E( BCDEE)=Z(3]5210535」58J0313230寸2+Q+8寸020°2523222220) F000001011010T110111101100 ABC 000 001 011 010 110 1111 101 100 4.BCE A.B.DE/BCEF ABCDF CDEFABCDE CABCDF ABEF BCDF A DEF A BCDE
3-5(d) 卡诺图化简 F(A,B,C,D,E,F) = m(3,7,12,14,15,19,23,27,28,29,31,35,39,44,45,46,48,49,50,52,53,55,56,57,59) DE F A BC 0 00 00 1 01 1 01 0 1 10 1 11 10 1 100 0 00 1 1 001 1 1 1 01 1 1 1 1 1 01 0 1 1 110 1 1 1 1 1 1 111 1 1 1 101 1 1 1 100 1 1 A B C E A B D E ABCDF B C EFABEFABCDF BCDF CDEF ADEF ABCDE ABCDE
3-9(a)用两个或非门实现 F=ABC+AbD+A bcd d= AbC +abD CD0001|1110 AB F=B.C+AB+B·D 001 1|=B(C+A+D) 01 =B(C +A+D) d 10 B+(C+A+D) A D F B
3-9(a) 用两个或非门实现 F = A B C + ABD + A BCD d = ABC + AB D C D A B 0 0 0 1 1 1 1 0 0 0 1 1 1 0 1 1 1 1 0 1 1 ( ) ( ) ( ) B C A D B C A D B C A D F B C AB B D = + + + = + + = + + = + + + + A B C D F
与或非门 ENTITY noand4 s PORT (a, b, c, d: IN BIT; y: OUT BIT END noand4 ARCHI TECTURE noand4 behavi of noand 4S BEGIN y<=NoT (a AND b) OR(c ANd d) AFTER 5ns END noand4 behav 1 ARCHI TECTURE noand4 behav2 OF noand4 S SIGNAL y1, y2, y3: BIT BEGIN y 1=a and b AFTER 5ns y 2<=c ANd d AFTER 5ns y 3=y 1 OR y2 AFTER 5ns y=NOT y 3 AFTER 5ns ENd noand4 behav 2
与或非门 ENTITY noand4 IS PORT （a,b,c,d:IN BIT;y:OUT BIT）； END noand4； ARCHITECTURE noand4_behav1 OF noand4 IS BEGIN y<=NOT (a AND b) OR (c AND d) AFTER 5ns； END noand4_behav1； ARCHITECTURE noand4_behav2 OF noand4 IS SIGNAL y1, y2, y3: BIT BEGIN y1<=a AND b AFTER 5ns； y2<=c AND d AFTER 5ns； y3<=y1 OR y2 AFTER 5ns； y<=NOT y3 AFTER 5ns； END noand4_behav2；
ARCHI TECTURE noand4 table of noand4 S BEGIN y<=′1′ When a ANDb=′1′ELSE WHEN C=′1′ANDd=′1′ELSE 0 End noand4 table: 异或门 ENTITY Or 2 S PorT (a, b: IN BIT: C: OUT BIT): END or 2; ARchi TECTURE xor 2 behav of xor 2 S BEGIN c<=a xor b aFter 5ns END xor 2 behav
ARCHITECTURE noand4_table OF noand4 IS BEGIN y<=′1′ WHEN a =′1′ AND b =′1′ELSE ′1′ WHEN c =′1′ AND d =′1′ELSE ′0′; END noand4_table； 异或门 ENTITY xor2 IS PORT （a,b:IN BIT;c:OUT BIT）； END xor2； ARCHITECTURE xor2_behav OF xor2 IS BEGIN c<=a XOR b AFTER 5ns； END xor2_behav；
ARCHITECTURE Or 2 sch of xor s SIGNAL y1, y2, y3, y4: BIT BeGiN y 1 =a ANd y2 AFTER 5ns; 2=not b After 5ns y 3=NOT a AFTER 5ns y4=b ANd y3 AFTER 5ns y=y4 oR y1 AFTER 5ns END Xor 2 sch: ARCHI TECTURE or 2 table of xor 2S BEGIN c<=′0′ WHEN a=′1′ANDb=′1′ELSE 0′ WhEN a=′0′ANDb=′0′ELSE END xor2 table
ARCHITECTURE xor2_sch OF xor2 IS SIGNAL y1, y2, y3, y4: BIT BEGIN y1<=a AND y2 AFTER 5ns； y2<=NOT b AFTER 5ns； y3<=NOT a AFTER 5ns； y4<=b AND y3 AFTER 5ns； y<=y4 OR y1 AFTER 5ns; END xor2_sch； ARCHITECTURE xor2_table OF xor2 IS BEGIN c<=′0′ WHEN a =′1′ AND b =′1′ELSE ′0′ WHEN a =′0′ AND b =′0′ELSE ′1′; END xor2_table；