1. architecture 体系结构 2. RISC Reduced Instruction set Computing 精简指令集计算技术 比较 CISC complex Instruction set Computing 复杂指令集计算技术

1.处理器 处理器是计算机的大脑。它也被称为微处理器或CPU。它解释从其它设备接收的全部 指令,并执行这些指令,如让打印机打印。一般来讲处理器的速度越快,计算机通常能够 执行指令和任务的速度就越快。这样,游戏可以玩得更顺畅,电子表格的运算可以进行得更快

Architecture of fleX device FastTrackTM Interconnect Same row LAB Copyright 1997 Altera Corporation

Asynchronous Circuit Design a Mainly use Combinational Logic to do the decoding Address decoder Fifo/Ram Read or Write pulse The output logic does not have any relationship with any clocking signal a Usually the Decoding Glitch can be monitored at the output signal

Design Files support by Maxtplus l Design File Entry Graphic Design File( GDF) Text Design Files(∵TDF) VHDL Design Files(*.VHD) EDIF Input Files (.EDF OrCad Schematic Files . SCH) Waveform Design Files *. WDF I You are allow to mix this design file with each other

If you were a If you were Altera Software Engineer, what shall you do? Graphic Entry H Graphic Compiler H Graphic processor VHDL Entry H VHDL Compiler H VHDL processor Fitting

What is combinational circuit Combinational circuit if Outputs at a specificed time are a function only of the INPUTS at that time example of combinational circuit address deco · addersders

Agenda What is FPGA Express? Design flow Design analysis FPGA Scripting Tool (fSt) Summary Verilog Coding Styles Tips Tricks

s the design simple enough to course any error? Any Setup/Hold time problem? ALBRA Copyright 1997 Altera Corporation

ClkI and Clk2 are the clock which running at different frequency Copyright 1997 Altera Corporation