康芯科技：《EDA技术实用教程》配套教学资源（PPT课件讲稿，第二版）第10章 设计优化和设计方法

EDA技术实用教程 第10章 设计优化和设计方法

第10章 设计优化和设计方法 EDA技术实用教程

2器时 10.1面积优化 10.1.1资源共享 AO B 0 Result Al 乘法器0 选择器 B 乘法器1 图10-1先乘后选择的设计方法RTL结构

康芯科技 10.1 面积优化 10.1.1 资源共享 乘法器0 × 乘法器1 × 选择器 0 1 Result Sel A0 B A1 B 图10-1先乘后选择的设计方法RTL结构

【例10-1】 2器时 LIBRARY ieee USE ieee std logic 1164 al: USE ieee std logic unsigned. all; USE ieee std logic arith. all ENTITY multmux Is PORT(AO, Al, B: IN std logic_ vector(3 downto 0); sel:in std logic Result OUT std logic vector(7 downto 0)); END multmux ARCHITECTURE rtl OF multmux IS BEGIN process(AO, Al, B, sel) begin if(sel =0)then Result <=A0* B else Result<=Al B: 图10-1先乘后选择的设计方法RTL结构 end if: end process; END rtl;

【例 康芯科技 10-1】 LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; ENTITYmultmux IS PORT (A0, A1，B :IN std_logic_vector(3 downto 0); sel : IN std_logic; Result : OUT std_logic_vector(7 downto 0)); END multmux; ARCHITECTURE rtl OF multmux IS BEGIN process(A0,A1,B,sel) begin if(sel = '0') then Result <= A0 * B; else Result <= A1 * B; 图10-1 先乘后选择的设计方法RTL结构 end if; end process; END rtl;

2器时 10.1面积优化 10.1.1资源共享 e A0 O Result 选择器 乘法器 图10-2先选择后乘设计方法RTL结构

康芯科技 10.1 面积优化 10.1.1 资源共享 图10-2先选择后乘设计方法RTL结构 选择器 0 1 乘法器 × A0 Sel A1 Result

2器时 10.1面积优化 10.1.1资源共享 【例10-2】 ARCHITECTURE rtl of muxmult Is signal temp: std logic vector(3 downto 0); BEGIN process(Ao, Al, B, sel) eg f(sel=0 )then temp<=A0; else temp<=Al; end if: result <=temp *B; nd process; END rtI:

康芯科技 10.1 面积优化 10.1.1 资源共享 【例10-2】 ARCHITECTURErtl OF muxmult IS signal temp : std_logic_vector(3 downto 0); BEGIN process(A0,A1,B,sel) begin if(sel = '0') then temp <= A0; else temp <= A1; end if; result <= temp * B; end process; END rtl;

2器时 10.1面积优化 10.1.1资源共享 0 R 0 R 选择器 B 选择器 R 图10-3资源共享反例 B 选择器

康芯科技 10.1 面积优化 10.1.1 资源共享 图10-3 资源共享反例 选择器 0 1 A B S R 选择器 0 1 A B S R 选择器 0 1 A B S R

10.1.2逻辑优化 2器时 【例10-3】 工工 BRARY eee; USE ieee std logic 1164. all use ieee std logic unsigned. al; use ieeestd logic arith. al; ENTITY multI is PORT(clk: in std logic ma: In std logic vector(ll downto 0); mc: out std logic vector(23 downto 0)); END multi ARChITECtURE rtI OF multI IS signal ta, tb std logic vector(11 downto 0); BEGIN process(clk) begin if(clk'event and clk='1)then ta<=ma;tb<="100l01l1001";mc<=ta*tb; end if end process: END rtI:

康芯科技 10.1.2 逻辑优化 【例10-3】 LIBRARY ieee; USE ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; ENTITY mult1 IS PORT(clk : in std_logic; ma : In std_logic_vector(11 downto 0); mc : out std_logic_vector(23 downto 0)); END mult1; ARCHITECTURE rtl OF mult1 IS signal ta，tb : std_logic_vector(11 downto 0); BEGIN process(clk) begin if(clk'event and clk = '1') then ta <= ma; tb <= "100110111001"; mc <= ta * tb; end if; end process; END rtl;

10.1.2逻辑优化 2器时 【例10-4】 LIBRARY Ieee; USE ieee std logic 1164.all use ieee std logic unsigned. all use ieee std logic arith. all; ENTITY muIt2 Is PORT(clk: in std logic ma: In std logic vector(1l downto 0); me: out std logic vector(23 downto 0); END multi: ARChITECTURE rtl OF mult2 IS signal ta: std logic vector(ll downto 0); constant tb: std logic vector(ll downto 0):100110111001 BEGIN process(clk) begin if(clk'event and clk='1)then ta<=ma; mc<=ta tb end if. end process; END rtI:

康芯科技 10.1.2 逻辑优化 【例10-4】 LIBRARY ieee; USE ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; ENTITY mult2 IS PORT(clk : in std_logic; ma : In std_logic_vector(11 downto 0); mc : out std_logic_vector(23 downto 0)); END mult2; ARCHITECTURE rtl OF mult2 IS signal ta : std_logic_vector(11 downto 0); constant tb : std_logic_vector(11 downto 0) := "100110111001"; BEGIN process(clk) begin if(clk'event and clk = '1') then ta<=ma; mc<=ta * tb; end if; end process; END rtl;

10.1.3串行化 2器时 【例10-5】 LIBRARY ieee; USE ieee std logic 1164. all; use ieee std logic unsigned. all use ieee std logic arith. all ENTITY pmultadd Is PORT(clk: in std logic a0, al, a2, a3: in std logic vector (7 downto O); b0, bl, b2, b3: in std logic vector(7 downto 0); yout out std logic vector(15 downto 0)); END pmultadd; ARCHITECTURE P arch OF pmultadd Is BEGIN process(clk) begin if(clk'event and clk=1")then yout <=((a0 b0)+(al* bl+((a2*b2)+(a3 b3)); end if; end process END P arch;

康芯科技 10.1.3 串行化 【例10-5】 LIBRARY ieee; USE ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; ENTITY pmultadd IS PORT(clk : in std_logic; a0,a1,a2,a3 : in std_logic_vector(7 downto 0); b0,b1,b2,b3 : in std_logic_vector(7 downto 0); yout : out std_logic_vector(15 downto 0)); END pmultadd; ARCHITECTURE p_arch OF pmultadd IS BEGIN process(clk) begin if(clk'event and clk = '1') then yout <= ((a0*b0)+(a1*b1))+((a2*b2)+(a3*b3)); end if; end process; END p_arch;

10.1.3串行化 2器时 3070 大 [150 b07000 1501 317000 150]150 b1700 :161:16 D15:0]Q15:0] 50150 yout[ 15: 0D 15:0 7[70 )150 5270 7070 3700 15:0 b3707 图10-4并行并行乘法RTL结构

康芯科技 10.1.3 串行化 [15:0] Q[15:0] [1:16] + D[15:0] [15:0] [15:0] [1:16] [15:0] [15:0] * [7:0] [15:0] [7:0] * [7:0] [15:0] [7:0] * [7:0] [15:0] [7:0] * [7:0] [15:0] [7:0] yout[15:0] [15:0] b3[7:0] [7:0] b2[7:0] [7:0] b1[7:0] [7:0] b0[7:0] [7:0] a3[7:0] [7:0] a2[7:0] [7:0] a1[7:0] [7:0] a0[7:0] [7:0] clk 图10-4 并行并行乘法RTL结构