查询MC1496供应商 MG1496,Mc1496B Balanced modulators ON Demodulators These devices were designed for use where the output voltage is a product of an input voltage(signal) and a switching function(carrier) ON Semiconductor Typical applications include suppressed carrier and amplitude modulation, synchronous detection, FM detection, phase detection, http:/lonsemi.com and chopper applications. See On Semiconductor Application Note an531 for additional design information. SOIC-14 D SUFFIX Features CASE 751A Excellent Carrier Suppression -65 dB typ(@0.5 MHz 50 dB typ@ 10 MHz Adjustable Gain and Signal Handling PDIP-14 Balanced Inputs and Outputs P SUFFⅨX High Common Mode Rejection -85 dB Typical CASE 646 e This device contains 8 active transistors Pb-Free Package is Available* PIN CONNECTIONS Signal Input 1 图v Gain Adjust 13N/C 21⑩ ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 12 of this data sheet DEVICE MARKING INFORMATION See general marking information in the device marking section on page 12 of this data sheet. and soldering details, please download the ON emiconductor Soldering and Mounting Techniques Reference Manual. SOLDERRM/D Publication Order Numb April, 2004--Rev 9 MC1496/D
Semiconductor Components Industries, LLC, 2004 April, 2004 − Rev. 9 1 Publication Order Number: MC1496/D MC1496, MC1496B Balanced Modulators/ Demodulators These devices were designed for use where the output voltage is a product of an input voltage (signal) and a switching function (carrier). Typical applications include suppressed carrier and amplitude modulation, synchronous detection, FM detection, phase detection, and chopper applications. See ON Semiconductor Application Note AN531 for additional design information. Features • Excellent Carrier Suppression −65 dB typ @ 0.5 MHz −50 dB typ @ 10 MHz • Adjustable Gain and Signal Handling • Balanced Inputs and Outputs • High Common Mode Rejection −85 dB Typical • This Device Contains 8 Active Transistors • Pb−Free Package is Available* http://onsemi.com SOIC−14 D SUFFIX CASE 751A 14 1 14 1 PDIP−14 P SUFFIX CASE 646 PIN CONNECTIONS Signal Input 1 2 3 4 5 6 7 10 11 14 13 12 9 N/C Output Bias Signal Input Gain Adjust Gain Adjust 8 Input Carrier VEE N/C Output N/C Carrier Input N/C See detailed ordering and shipping information in the package dimensions section on page 12 of this data sheet. ORDERING INFORMATION See general marking information in the device marking section on page 12 of this data sheet. DEVICE MARKING INFORMATION *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 查询MC1496供应商
Mc1496,Mc1496B =10kH Ic= 500 kHz, Is= 1.0 kHz Figure 1. Suppressed Carrier Output Figure 2. Suppressed Carrier Spectrum Waveform ls= 1.0 kHz 499 KHz 500 KHz 501 KHZ Figure 3. Amplitude Modulation Figure 4. Amplitude-Modulation Spectrum Output Waveform MAXIMUM RATINGS (TA= 25.C, unless otherwise noted Rating Symbol Unit 6-V8,v10V1,v12-V8,V12-V10,v8-V4.V8-V1,V10-V4,v6-V10.V2-V5,V3-V5) Differential Input Signal v8-V10 +5.0 Vdc 4-V1±5+15Re) Maximum Bias Current l5 Thermal Resistance. Junction-to -Air R 100 Plastic Dual In-Line Package Operating Ambient Temperature Range MC1496 0to+70°c MC1496B -40to+125 Storage Temperature Range sg|-65to+150° Electrostatic Discharge Sensitivity(ESD) man Body Model(HBM) 2000 Machine Model (MM) Maximum ratings are those values beyond which device damage can occur. Maxi values(not nomal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation i not implied damage may occur and reliability may be affected. httpllonsemi.com
MC1496, MC1496B http://onsemi.com 2 IC = 500 kHz, IS = 1.0 kHz IC = 500 kHz IS = 1.0 kHz 60 40 20 0 Log Scale Id 499 kHz 500 kHz 501 kHz IC = 500 kHz IS = 1.0 kHz IC = 500 kHz IS = 1.0 kHz 499 kHz 500 kHz 501 kHz Linear Scale 10 8.0 6.0 4.0 2.0 0 Figure 1. Suppressed Carrier Output Waveform Figure 2. Suppressed Carrier Spectrum Figure 3. Amplitude Modulation Output Waveform Figure 4. Amplitude−Modulation Spectrum MAXIMUM RATINGS (TA = 25°C, unless otherwise noted.) Rating Symbol Value Unit Applied Voltage (V6−V8, V10−V1, V12−V8, V12−V10, V8−V4, V8−V1, V10−V4, V6−V10, V2−V5, V3−V5) V 30 Vdc Differential Input Signal V8 − V10 V4 − V1 +5.0 ±(5+I5Re) Vdc Maximum Bias Current I5 10 mA Thermal Resistance, Junction−to−Air Plastic Dual In−Line Package RJA 100 °C/W Operating Ambient Temperature Range MC1496 MC1496B TA 0 to +70 −40 to +125 °C Storage Temperature Range Tstg −65 to +150 °C Electrostatic Discharge Sensitivity (ESD) Human Body Model (HBM) Machine Model (MM) ESD 2000 400 V Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.
Mc1496,Mc1496B ELECTRICAL CHARACTERISTICS (Vcc=12 Vdc, VEE=-80 Vdc, 15=1.0 mAdc, RL=3.9 k@2, R,=1.0 k@, TA=Tlow to Thigh, all input and output characteristics are single-ended, unless otherwise noted )(Note 1) Characteristic Fig.Note Symbol Min Typ MaxUnit Carrier Feedthrough uVms Vc=60 mVrms sine wave and fc=1.0 kHz offset adjusted to zer fc =10 MHz Vc=300 mVpp square wave: offset adjusted to zero fc =1.0 kHz offset not adjusted CS fc 500 kHz, 60 mVrms sine wave 65 fc= 10 MHz, 60 mVm Transadmittance Bandwidth(Magnitude)(Rl= 50 2) Carrier Input Port, Vc=60 mVrms sine wave Signal Input Port, Vs= 300 mVrms sine wave 80 Vcl =0.5 Vdc Signal Gain (Vs= 100 mVrms, f=1.0 kHz; VCl= 0. 5 Vdc) 3 2535 Single-Ended Input Impedance, Signal Port, f= 5.0 MHz Parallel Input Capacitance p Parallel Output Resistance Parallel Output Capacitance 50 Input Bias Current Input Offset Current 0.7 los=11-4;loc=8-110 0770 Average Temperature Coefficient of Input Offset Current ITCliol 2.0 DAC TA=-55cto+125°C) Output Offset Current(16-19) Average Temperature Coefficient of Output Offset Current TclooI (TA=-55Cto+125°C) Common-Mode Input Swing, Signal Port, fs=1.0 kHz Common-Mode Gain, Signal Port, fs =1.0 kHz, Ncl= 0.5 vdc ACM Common-Mode Quiescent Output Voltage(Pin 6 or Pin 9) Differential Output Voltage Swing Capability Power Supply Current 16+112 Icc 14 3050 DC Power Dissipa 1. Tlow =0C for MC1496 Thigh -+125C for MC1496B =+70° for mc1496 40C for MC1496B httpllonsemi.com
MC1496, MC1496B http://onsemi.com 3 ELECTRICAL CHARACTERISTICS (VCC = 12 Vdc, VEE = −8.0 Vdc, I5 = 1.0 mAdc, RL = 3.9 k, Re = 1.0 k, TA = Tlow to Thigh, all input and output characteristics are single−ended, unless otherwise noted.) (Note 1) Characteristic Fig. Note Symbol Min Typ Max Unit Carrier Feedthrough VC = 60 mVrms sine wave and offset adjusted to zero VC = 300 mVpp square wave: offset adjusted to zero offset not adjusted fC = 1.0 kHz fC = 10 MHz fC = 1.0 kHz fC = 1.0 kHz 5 1 VCFT − − − − 40 140 0.04 20 − − 0.4 200 Vrms mVrms Carrier Suppression fS = 10 kHz, 300 mVrms fC = 500 kHz, 60 mVrms sine wave fC = 10 MHz, 60 mVrms sine wave 5 2 VCS 40 − 65 50 − − dB k Transadmittance Bandwidth (Magnitude) (RL = 50 ) Carrier Input Port, VC = 60 mVrms sine wave fS = 1.0 kHz, 300 mVrms sine wave Signal Input Port, VS = 300 mVrms sine wave |VC| = 0.5 Vdc 8 8 BW3dB − − 300 80 − − MHz Signal Gain (VS = 100 mVrms, f = 1.0 kHz; |VC|= 0.5 Vdc) 10 3 AVS 2.5 3.5 − V/V Single−Ended Input Impedance, Signal Port, f = 5.0 MHz Parallel Input Resistance Parallel Input Capacitance 6 − rip cip − − 200 2.0 − − k pF Single−Ended Output Impedance, f = 10 MHz Parallel Output Resistance Parallel Output Capacitance 6 − rop coo − − 40 5.0 − − k pF Input Bias Current 7 − I 12 30 A I bS I1 I4 2 ; IbC I8 I10 2 IbS IbC − − 12 12 30 30 Input Offset Current IioS = I1−I4; IioC = I8−I10 7 − IioS IioC − − 0.7 0.7 7.0 7.0 A Average Temperature Coefficient of Input Offset Current (TA = −55°C to +125°C) 7 − TCIio − 2.0 − nA/°C Output Offset Current (I6−I9) 7 − Ioo − 14 80 A Average Temperature Coefficient of Output Offset Current (TA = −55°C to +125°C) 7 − TCIoo − 90 − nA/°C Common−Mode Input Swing, Signal Port, fS = 1.0 kHz 9 4 CMV − 5.0 − Vpp Common−Mode Gain, Signal Port, fS = 1.0 kHz, |VC|= 0.5 Vdc 9 − ACM − −85 − dB Common−Mode Quiescent Output Voltage (Pin 6 or Pin 9) 10 − Vout − 8.0 − Vpp Differential Output Voltage Swing Capability 10 − Vout − 8.0 − Vpp Power Supply Current I6 +I12 Power Supply Current I14 7 6 ICC IEE − − 2.0 3.0 4.0 5.0 mAdc DC Power Dissipation 7 5 PD − 33 − mW 1. Tlow = 0°C for MC1496 Thigh = +70°C for MC1496 = −40°C for MC1496B = +125°C for MC1496B
Mc1496,Mc1496B GENERAL OPERATING INFORMATION Carrier Feedthrough Note that in the test circuit of Figure 10, Vs corresponds to Carrier feedthrough is defined as the output voltage at a maximum value of 1.0 V peak arrier frequency with only the carrier applied Common Mode Swing Carrier null is achieved by balancing the currents in the The common-mode swing is the voltage which may be (e terential amplifier by means of a bias trim potentiometer applied to both bases of the signal differential amplifier, without saturating the current sources or without saturating the differential amplifier itself by swinging it into the upper Carrier Suppression switching devices. This swing is variable depending on the Carrier suppression is defined as the ratio of each particular circuit and biasing conditions chosen ideband output to carrier output for the carrier and signal voltage levels specified Power Dissipation Carrier suppression is very dependent on carrier input Power dissipation, PD, within the integrated circuit level, as shown in Figure 22. A low value of the carrier does package should be calculated as the summation of the not fully switch the upper switching devices, and results in voltage current products at each port,i.e.assuming lower signal gain, hence lower carrier suppression. A higher than optimum carrier level results in unnecessary device and PD 2 15(V6-V14)+ 15)V5-V14 where subscripts refer circuit carrier feedthrough, which again degenerates the to pin numbers suppression figure. The MC1496 has been characterized Design Equations with a 60 m Vrms sinewave carrier input signal. This level provides optimum carrier suppression at carrier frequencies The following is a partial list of design equations needed in the vicinity of 500 kHz, and is generally recommended for to operate the circuit with other supply voltages and input conditions balanced modulator applications Carrier feedthrough is independent of signal level, V A. Operating Current Thus carrier suppression can be maximized by operating The internal bias currents are set by the conditions at Pin 5 with large signal levels. However, a linear operating mode must be maintained in the signal-input transistor pair-or 15=16=112, harmonics of the modulating signal will be generated and IB<<Ic for all transistors appear in the device output as spurious sidebands of the then suppressed carrier. This requirement places an upper limit optimum carrier level is recommended in Figure 22 for good -15-5002 where: R5 is the resistor between on input-signal amplitude(see Figure 20). Note also that an Pin 5 and ground carrier suppression and minimum spurious sideband φ=075atTA=+25°C generation The MC1496 has been characterized for the condition At higher frequencies circuit layout is very important in 15=1.0 mA and is the generally recommended value order to minimize carrier feedthrough Shielding may be B Common-Mode Quiescent Output Voltage necessary in order to prevent capacitive coupling between V6=V12=V+-15RL the carrier input leads and the output lead Signal Gain and Maximum Input Level Biasing Signal gain(single-ended)at low frequencies is defined The MC1496 requires three dc bias voltage levels which as the voltage gain, must be set externally. Guidelines for setting up these three levels include maintaining at least 2.0 V collector-base bias on all transistors while not exceeding the voltages given in where re the absolute maximum rating table 30vdc≥[(v6,V12)-(V8,v1O≥2Vdc A constant dc potential is applied to the carrier input 30vdc≥[(v8,V10)-(V1,V4)≥2.7vdc terminals to fully switch two of the upper transistors"on 30vdc≥[(v1,V4)-(V5)≥2.7vdc and two transistors"off"(Ve=0.5 Vdc). This in effect The foregoing conditions are based on the following forms a cascode differential amplifier critical value determined by Re and the bias current 5a approximations Linear operation requires that the signal input be below 6=V12,v8=V10,V1=V4 httpllonsemi.com
MC1496, MC1496B http://onsemi.com 4 GENERAL OPERATING INFORMATION Carrier Feedthrough Carrier feedthrough is defined as the output voltage at carrier frequency with only the carrier applied (signal voltage = 0). Carrier null is achieved by balancing the currents in the differential amplifier by means of a bias trim potentiometer (R1 of Figure 5). Carrier Suppression Carrier suppression is defined as the ratio of each sideband output to carrier output for the carrier and signal voltage levels specified. Carrier suppression is very dependent on carrier input level, as shown in Figure 22. A low value of the carrier does not fully switch the upper switching devices, and results in lower signal gain, hence lower carrier suppression. A higher than optimum carrier level results in unnecessary device and circuit carrier feedthrough, which again degenerates the suppression figure. The MC1496 has been characterized with a 60 mVrms sinewave carrier input signal. This level provides optimum carrier suppression at carrier frequencies in the vicinity of 500 kHz, and is generally recommended for balanced modulator applications. Carrier feedthrough is independent of signal level, VS. Thus carrier suppression can be maximized by operating with large signal levels. However, a linear operating mode must be maintained in the signal−input transistor pair − or harmonics of the modulating signal will be generated and appear in the device output as spurious sidebands of the suppressed carrier. This requirement places an upper limit on input−signal amplitude (see Figure 20). Note also that an optimum carrier level is recommended in Figure 22 for good carrier suppression and minimum spurious sideband generation. At higher frequencies circuit layout is very important in order to minimize carrier feedthrough. Shielding may be necessary in order to prevent capacitive coupling between the carrier input leads and the output leads. Signal Gain and Maximum Input Level Signal gain (single−ended) at low frequencies is defined as the voltage gain, AVS Vo VS RL Re2re where re 26 mV I5(mA) A constant dc potential is applied to the carrier input terminals to fully switch two of the upper transistors “on” and two transistors “off” (VC = 0.5 Vdc). This in effect forms a cascode differential amplifier. Linear operation requires that the signal input be below a critical value determined by RE and the bias current I5. VS I5 RE (Volts peak) Note that in the test circuit of Figure 10, VS corresponds to a maximum value of 1.0 V peak. Common Mode Swing The common−mode swing is the voltage which may be applied to both bases of the signal differential amplifier, without saturating the current sources or without saturating the differential amplifier itself by swinging it into the upper switching devices. This swing is variable depending on the particular circuit and biasing conditions chosen. Power Dissipation Power dissipation, PD, within the integrated circuit package should be calculated as the summation of the voltage−current products at each port, i.e. assuming V12 = V6, I5 = I6 = I12 and ignoring base current, PD = 2 I5 (V6 − V14) + I5)V5 − V14 where subscripts refer to pin numbers. Design Equations The following is a partial list of design equations needed to operate the circuit with other supply voltages and input conditions. A. Operating Current The internal bias currents are set by the conditions at Pin 5. Assume: I5 = I6 = I12, IBIC for all transistors then : R5V I5 500 where: R5 is the resistor between where: Pin 5 and ground where: = 0.75 at TA = +25°C The MC1496 has been characterized for the condition I5 = 1.0 mA and is the generally recommended value. B. Common−Mode Quiescent Output Voltage V6 = V12 = V+ − I5 RL Biasing The MC1496 requires three dc bias voltage levels which must be set externally. Guidelines for setting up these three levels include maintaining at least 2.0 V collector−base bias on all transistors while not exceeding the voltages given in the absolute maximum rating table; 30 Vdc [(V6, V12) − (V8, V10)] 2 Vdc 30 Vdc [(V8, V10) − (V1, V4)] 2.7 Vdc 30 Vdc [(V1, V4) − (V5)] 2.7 Vdc The foregoing conditions are based on the following approximations: V6 = V12, V8 = V10, V1 = V4
Mc1496,Mc1496B Bias currents flowing into Pins 1. 4. 8 and 10 are transistor base currents and can normally be neglected if external bias VEE Should be dc only. The insertion of an RF choke in dividers are designed to carry 1.0 ma or more series with Vee can enhance the stability of the internal current sources Transadmittance Bandwidth Carrier transadmittance bandwidth is the 3.0 dB bandwidth Signal Port Stability of the device forward transadmittance as defined by Under certain values of driving source impedance Y21C<o(each sideband) oscillation may occur. In this event, an RC suppression Vo=0 network should be connected directly to each input using hort leads. This will reduce the Q of the source-tuned Signal transadmittance bandwidth is the 3.0 dB bandwidth circuits that cause the oscillation of the device forward transadmittance as defined by (signal) Y21Sv(signal Ivc=0.5 Vdc, Vo=o (Pins 1 and 4) Coupling and Bypass Capacitors Capacitors CI and C2 (Figure 5)should be selected for a reactance of less than 5.0 $2 at the carrier frequency An alternate method for low-frequency applications is to Output signal insert a 1.0 k9 resistor in series with the input(Pins 1, 4). In The output signal is taken from Pins 6 and 12 either this case input current drift may cause serious degradation balanced or single-ended Figure lI shows the output levels of carrier suppression of each of the two output sidebands resulting from variations in both the carrier and modulating signal inputs with a single-ended output connection TEST CIRCUITS 12 Vdc 1.0k Re=1.0k 0.1uF T Carrier 0.1 uF Mc1496 Zina MC1496 14 10k10k5 14 1568k Carrier nul -8.0 Vdc Figure 5. Carrier Rejection and Suppression Figure 6. Input-Output Impedance 10k 12 Vdc .0k 01证木 20k Carrier 1.0k Mc1496 Mc14966 Modulating 14 50k Carrier null 8.0 Vdc -8.0 Vdc VEE Figure 7. Bias and Offset Currents Figure 8. Transconductance Bandwidth httpllonsemi.com
MC1496, MC1496B http://onsemi.com 5 Bias currents flowing into Pins 1, 4, 8 and 10 are transistor base currents and can normally be neglected if external bias dividers are designed to carry 1.0 mA or more. Transadmittance Bandwidth Carrier transadmittance bandwidth is the 3.0 dB bandwidth of the device forward transadmittance as defined by: 21C i o (each sideband) vs (signal) Vo 0 Signal transadmittance bandwidth is the 3.0 dB bandwidth of the device forward transadmittance as defined by: 21S i o (signal) vs (signal) Vc 0.5 Vdc, Vo 0 Coupling and Bypass Capacitors Capacitors C1 and C2 (Figure 5) should be selected for a reactance of less than 5.0 at the carrier frequency. Output Signal The output signal is taken from Pins 6 and 12 either balanced or single−ended. Figure 11 shows the output levels of each of the two output sidebands resulting from variations in both the carrier and modulating signal inputs with a single−ended output connection. Negative Supply VEE should be dc only. The insertion of an RF choke in series with VEE can enhance the stability of the internal current sources. Signal Port Stability Under certain values of driving source impedance, oscillation may occur. In this event, an RC suppression network should be connected directly to each input using short leads. This will reduce the Q of the source−tuned circuits that cause the oscillation. Signal Input (Pins 1 and 4) 510 10 pF An alternate method for low−frequency applications is to insert a 1.0 k resistor in series with the input (Pins 1, 4). In this case input current drift may cause serious degradation of carrier suppression. NOTE: Shielding of input and output leads may be needed to properly perform these tests. Figure 5. Carrier Rejection and Suppression Figure 6. Input−Output Impedance Figure 7. Bias and Offset Currents Figure 8. Transconductance Bandwidth 0.01 F 2.0 k −8.0 Vdc I6 I9 1.0 k I7 I8 6.8 k Zout +Vo + +Vo I9 3 RL 3.9 k VCC 12 Vdc 8 C1 0.1 F MC1496 1.0 k 2 Re 1.0 k C2 0.1 F 51 10 k Modulating Signal Input Carrier InputVC Carrier Null 10 k 51 51 50 k R1 VS −Vo RL 3.9 k I6 I4 6 14 5 12 − 2 Re = 1.0 k 3 Zin 0.5 V 8 10 I1 4 1 10 −Vo 1 6 4 14 5 12 6.8 k V− I10 I5 −8.0 Vdc VEE 1.0 k MC1496 MC1496 6 MC1496 14 5 12 I10 6.8 k −8.0 Vdc VEE VCC 12 Vdc 2 Re = 1.0 k 3 1.0 k Modulating Signal Input Carrier Input VC VS 0.1 F 0.1 F 1.0 k 51 1.0 k 14 5 6 12 1.0 k 2 3 Re VCC 12 Vdc 2.0 k +Vo −Vo 6.8 k 10 k Carrier Null 10 k 51 50 k V− −8.0 Vdc VEE 50 50 8 10 4 1 8 10 4 1 51 TEST CIRCUITS
Mc1496,Mc1496B Re=1.0k 39k39k 39k39k 1.0k Mc1496 Mc14966 50 -8.0 Vdc Figure 9. Common Mode gain Figure 10. Signal Gain and Output Swing TYPICAL CHARACTERISTICS Typical characteristics were obtained with circuit shown in Figure 5, fc 500 kHz(sine wave) Vc=60 mVrms, fs =1.0 kHz, Vs= 300 mVrms, TA= 25C, unless otherwise note 220 5u55 Signal Input= 600 mv 兰u2与z 0.8 300mV 0.4 彐50 50 Vc, CARRIER LEVEL(mVr f, FREQUENCY(MHz) Figure 12. Signal-Port Parallel-Equivalent Carrier Levels Input Resistance versus Frequency 5.0 ■■ ■■ suzoo2 □LLI ■I ■■ 10 f, FREQUENCY(MHz) Figure 13. Signal-Port Parallel-Equivalent Figure 14 Single-Ended Output Impedance versus Frequency
MC1496, MC1496B http://onsemi.com 6 +Vo 3 3.9 k VCC 12 Vdc 8 MC1496 2 Re = 1.0 k 1.0 k 0.5 V 1.0 k 50 + VS −Vo 10 1 6 4 14 5 12 6.8 k −8.0 Vdc VEE 3.9 k − ACM 20 log Vo VS Figure 9. Common Mode Gain Figure 10. Signal Gain and Output Swing V , OUTPUT AMPLITUDE OF EACH SIDEBAND (Vrms) O r , PARALLEL INPUT RESISTANCE (k ip Figure 11. Sideband Output versus Carrier Levels Figure 12. Signal−Port Parallel−Equivalent Input Resistance versus Frequency c , PARALLEL INPUT CAPACITANCE (pF) ip c , PARALLEL OUTPUT CAPACITANCE (pF) op Figure 13. Signal−Port Parallel−Equivalent Input Capacitance versus Frequency Figure 14. Single−Ended Output Impedance versus Frequency TYPICAL CHARACTERISTICS Typical characteristics were obtained with circuit shown in Figure 5, fC = 500 kHz (sine wave), VC = 60 mVrms, fS = 1.0 kHz, VS = 300 mVrms, TA = 25°C, unless otherwise noted. I5 = 1.0 mA +Vo 3 3.9 k VCC 12 Vdc 2 Re = 1.0 k −Vo 6 14 5 12 6.8 k −8.0 Vdc VEE 3.9 k 0.5 V + − 1.0 k 1.0 k VS 50 1.0 2.0 0 140 −rip +rip 14 12 10 8.0 6.0 4.0 0 10 100 120 0 10 1.0 20 5.0 100 40 50 1.0 1.0 f, FREQUENCY (MHz) 80 200 2.0 5.0 10 100 100 500 1.0 M 60 50 2.0 10 100 3.0 2.0 1.0 0 5.0 400 mV Signal Input = 600 mV 4.0 VC, CARRIER LEVEL (mVrms) 1.6 0 0.8 0 0.4 1.2 50 150 100 5.0 100 mV 200 mV 300 mV 20 50 f, FREQUENCY (MHz) f, FREQUENCY (MHz) MC1496 8 10 1 4 rop Ω) r , PARALLEL OUTPUT RESISTANCE (k op Ω) cop
Mc1496,Mc1496B TYPICAL CHARACTERISTICS (continued) ypical characteristics were obtained with circuit shown in Figure 5. fc= 500 kHz(sine wave) mVrms, fs= 1.0 kHZ, Vs= 300 mVms, TA= 25C, unless otherwise noter 10 Ez MC1496 lout Each Sideband) §50 0.1 in /out =0/ 75-50-2 255075100125150175 fc, CARRIER FREQUENCY(MHz) TA, AMBIENT TEMPERATURE(C) Figure 15. Sideband and Signal Port Figure 16. Carrier Suppression Transadmittance versus Frequency 巴至u 20 RL=3.9 k(Standard 1.0 k Test Circuit) Re=2.0 k Vcl=0.5 Vdc ft廿 f, FREQUENCY (MHz) fc, CARRIER FREQUENCY (MHz) Figure 17 Signal-Port Frequency Response igure 18. Carrier Suppression versus Frequ 「「丰 聿目 §8如/ tc± a70 80 0050.1 fc, CARRIER FREQUENCY(MHz) Vs, INPUT SIGNAL AMPLITUDE (mVrms Figure 19. Carrier Feedthrough Figure 20 Sideband Harmonic Suppression versus Frequency versus Input signal Level httpllonsemi.com
MC1496, MC1496B http://onsemi.com 7 −30 f, FREQUENCY (MHz) 20 10 0 −10 −20 0.01 0.1 1.0 10 100 RL = 3.9 k Re = 500 RL = 3.9 k Re = 2.0 k |VC| = 0.5 Vdc RL = 500 Re = 1.0 k RL = 3.9 k (Standard Re = 1.0 k Test Circuit) A , SINGLE-ENDED VOLTAGE GAIN (dB) VS 1.0 100 Side Band 0.3 0.4 0 1000 fC, CARRIER FREQUENCY (MHz) 0.6 0.9 1.0 10 0.8 0.7 0.1 0.2 0.5 0.1 21, TRANSADMITTANCE (mmho) 80 0 fC ± 3fS 200 400 600 800 VS, INPUT SIGNAL AMPLITUDE (mVrms) fC ± 2fS 0 60 50 40 30 20 10 70 SUPPRESSION BELOW EACH FUNDAMENTAL CARRIER SIDEBAND (dB) fC 2fC 0.05 0.1 0.5 1.0 10 5.0 50 3fC 0 60 50 40 30 20 10 70 fC, CARRIER FREQUENCY (MHz) SUPPRESSION BELOW EACH FUNDAMENTAL CARRIER SIDEBAND (dB) TA, AMBIENT TEMPERATURE (°C) MC1496 (70°C) −75 −50 60 −25 0 25 50 75 50 40 30 20 10 100 125 150 175 70 CS V , CARRIER SUPPRESION (dB) AV RL Re 2re TYPICAL CHARACTERISTICS (continued) Typical characteristics were obtained with circuit shown in Figure 5, fC = 500 kHz (sine wave), VC = 60 mVrms, fS = 1.0 kHz, VS = 300 mVrms, TA = 25°C, unless otherwise noted. 0.1 10 50 10 1.0 0.01 0.05 0.1 0.5 1.0 5.0 fC, CARRIER FREQUENCY (MHz) V , CARRIER OUTPUT VOLTAGE (mVrms) CFT Signal Port 0 Figure 15. Sideband and Signal Port Transadmittances versus Frequency Figure 16. Carrier Suppression versus Temperature Figure 17. Signal−Port Frequency Response Figure 18. Carrier Suppression versus Frequency Figure 19. Carrier Feedthrough versus Frequency Figure 20. Sideband Harmonic Suppression versus Input Signal Level γ 21 I out Vin Vout 0|VC| 0.5Vdc 21 I out(EachSideband) Vin(Signal) Vout 0 Sideband Transadmittance Signal Port Transadmittance
Mc1496,Mc1496B 60 60 fc, CARRIER FREQUENCY(MHz) Vc, CARRIER INPUT LEVEL (mVms Figure 21. Suppression of Carrier Harmonic Figure 22. Carrier Suppression versus Sidebands versus Carrier Frequency Carrier Input Level OPERATIONS INFORMATION The MC1496, a monolithic balanced modulator circuit, is components and have an amplitude which is a function of the shown in Figure 23 product of the input signal amplitudes o This circuit consists of an upper quad differential amplifier For high-level operation at the carrier input port and riven by a standard differential amplifier with dual current linear operation at the modulating signal port, the output sources. The output collectors are cross coupled so that signal will contain sum and difference frequency full-wave balanced multiplication of the two input voltages components of the modulating signal frequency and the occurs. That is, the output signal is a constant times the fundamental and odd harmonics of the carrier frequency product of the two input signals The output amplitude will be a constant times the Mathematical analysis of linear ac signal multiplication modulating signal amplitude. Any amplitude variations in dicates that the output spectrum will consist of only the sum the carrier signal will not appear in the output and difference of the two input frequencies. Thus, the device The linear signal handling capabilities of a differential may be used as a balanced modulator, doubly balanced mixer, amplifier are well defined. With no emitter degeneration, the product detector, frequency doubler, and other applications maximum input voltage for linear operation is requiring these particular output signal characteristics approximately 25 mv peak. Since the upper differential The lower differential amplifier has its emitters connected amplifier has its emitters internally connected, this voltage to the package pins so that an external emitter resistance may applies to the carrier input port for all conditions be used. Also, external load resistors are employed at the Since the lower differential amplifier has provisions for an external emitter resistance. its linear signal handling range may be adjusted by the user. The maximum input voltage for Signal Levels linear operation may be approximated from the following The upper quad differential amplifier may be operated either in a linear or a saturated mode. the lower differential expression amplifier is operated in a linear mode for most applications V=( 5(RE) volts peak For low-level operation at both input ports, the output This expression may be used to compute the minimum ignal will contain sum and difference frequency value of RE for a given input voltage amplitude (-) R10k93 39k339k 1Mc1496 Signal 10k Bias 5 5568k 500 per G Carrier null Figure 23 Circuit Schematic Figure 24. Typical Modulator Circuit http://onsemi.com
MC1496, MC1496B http://onsemi.com 8 0 200 100 400 300 500 VC, CARRIER INPUT LEVEL (mVrms) fC = 10 MHz 0 60 50 40 30 20 10 70 CS V , CARRIER SUPPRESSION (dB) 2fC ± fS 2fC ± 2fS 3fC ± fS fC, CARRIER FREQUENCY (MHz) 0.05 0.1 0.5 1.0 5.0 10 50 0 60 50 40 30 20 10 70 SUPPRESSION BELOW EACH FUNDAMENTAL CARRIER SIDEBAND (dB) Figure 21. Suppression of Carrier Harmonic Sidebands versus Carrier Frequency Figure 22. Carrier Suppression versus Carrier Input Level fC = 500 kHz OPERATIONS INFORMATION The MC1496, a monolithic balanced modulator circuit, is shown in Figure 23. This circuit consists of an upper quad differential amplifier driven by a standard differential amplifier with dual current sources. The output collectors are cross−coupled so that full−wave balanced multiplication of the two input voltages occurs. That is, the output signal is a constant times the product of the two input signals. Mathematical analysis of linear ac signal multiplication indicates that the output spectrum will consist of only the sum and difference of the two input frequencies. Thus, the device may be used as a balanced modulator, doubly balanced mixer, product detector, frequency doubler, and other applications requiring these particular output signal characteristics. The lower differential amplifier has its emitters connected to the package pins so that an external emitter resistance may be used. Also, external load resistors are employed at the device output. Signal Levels The upper quad differential amplifier may be operated either in a linear or a saturated mode. The lower differential amplifier is operated in a linear mode for most applications. For low−level operation at both input ports, the output signal will contain sum and difference frequency components and have an amplitude which is a function of the product of the input signal amplitudes. For high−level operation at the carrier input port and linear operation at the modulating signal port, the output signal will contain sum and difference frequency components of the modulating signal frequency and the fundamental and odd harmonics of the carrier frequency. The output amplitude will be a constant times the modulating signal amplitude. Any amplitude variations in the carrier signal will not appear in the output. The linear signal handling capabilities of a differential amplifier are well defined. With no emitter degeneration, the maximum input voltage for linear operation is approximately 25 mV peak. Since the upper differential amplifier has its emitters internally connected, this voltage applies to the carrier input port for all conditions. Since the lower differential amplifier has provisions for an external emitter resistance, its linear signal handling range may be adjusted by the user. The maximum input voltage for linear operation may be approximated from the following expression: V = (I5) (RE) volts peak. This expression may be used to compute the minimum value of RE for a given input voltage amplitude. Signal Input Carrier Input 8 (+) 500 500 500 VEE 14 Bias VC (Pin numbers per G package) Vo, Output (−) 12 2 Gain Adjust 3 (+) 6 VS 10 (−) 4 (−) 1 (+) 5 −Vo 2 Re 1.0 k 12 Vdc RL 3.9 k +Vo VEE −8.0 Vdc 6.8 k I5 14 0.1 F 12 MC1496 6 8 1.0 k 1.0 k 50 k 51 10 k 10 k 0.1 F Carrier Input Modulating Signal Input VS VC Carrier Null 51 3 51 4 1 10 5 RL 3.9 k Figure 23. Circuit Schematic Figure 24. Typical Modulator Circuit
Mc1496,Mc1496B able 1. voltage Gain and output Frequencies Carrier Input Signal (Vc) Approximate Voltage Gain Output signal Frequency(s) LOw-level dc () fM High-level dc RL RLC(ms) LOw-level ac 22(x)(R=+2e fc±f 0637R 毛±fM,3fc±fMs,5fc±f 4. All gain expressions are for a single-ended output. For a differential output connection, multiply each expression by two esista 7. tE Transistor dynamic emitter resistance, at 25G re=26 mv es Kelvin, q= the charg The gain from the modulating signal input port to the All that is required to shift from suppressed carrier to AM output is the MC1496 gain parameter which is most often of operation is to adjust the carrier null potentiometer for the interest to the designer. This gain has significance only when proper amount of carrier insertion in the output signal the lower differential amplifier is operated in a linear mode However, the suppressed carrier null circuitry as shown in es most applications of the dev Figure 26 does not have sufficient adjustment range As previously mentioned, the upper quad differential Therefore, the modulator may be modified for AM amplifier may be operated either in a linear or a saturated operation by changing two resistor values in the null circuit mode. Approximate gain expressions have been developed as shown in Figure 27 for the MC1496 for a low-level modulating signal input and the following carrier input conditions Product Detector 1)Low-level dc The MC1496 makes an excellent SSB product detector 2)High-level dc (see Figure 28) 3)Low-level ac This product detector has a sensitivity of 3.0 uV and a 4)High-level ac dynamic range of 90 dB when operating at an intermediate frequency of 9.0 MHz basic application of the MC1496. The suggested circuit for amplifier input impedan k as o"% These gains are summarized in Table 1, along with the The detector is broadband for the entire high frequency frequency components contained in the output signal range For operation at very low down to 50 kHz the 0. 1 uF capacitors on Pins 8 and 10 should APPLICATIONS INFORMATION be increased to 1.0 uF. Also, the output filter at Pin 12 can Double sideband suppressed carrier modulation is the be tailored to a specific intermediate frequency and audio this application is shown on the front page of this data sheet. As in all applications of the MC1496, the emitter In some applications, it may be necessary to operate the resistance between Pins 2 and 3 may be increased or MC1496 with a single dc supply voltage instead of dual decreased to adjust circuit gain, sensitivity, and dynamic supplies. Figure 25 shows a balanced modulator designed range for operation with a single 12 Vdc supply Performance of this circuit is similar to that of the dual supply modulat introducing carrier signal at the carrier input and an AM AM Modulator signal at the SSB input The carrier signal may be derived from the intermediate The circuit shown in Figure 26 may be used as an frequency signal or generated locally. The carrier signal may mplitude modulator with a minor modification httpllonsemi.com
MC1496, MC1496B http://onsemi.com 9 Table 1. Voltage Gain and Output Frequencies Carrier Input Signal (VC) Approximate Voltage Gain Output Signal Frequency(s) Low−level dc RL VC 2(RE 2re) KT q fM High−level dc RL RE 2re fM Low−level ac RL VC(rms) 2 2 KT q (RE 2re) fC ± fM High−level ac 0.637 RL RE 2re fC ± fM, 3fC ± fM, 5fC ± fM, . . . 2. Low−level Modulating Signal, VM, assumed in all cases. VC is Carrier Input Voltage. 3. When the output signal contains multiple frequencies, the gain expression given is for the output amplitude ofeach of the two desired outputs, fC + fM and fC − fM. 4. All gain expressions are for a single−ended output. For a differential output connection, multiply each expression by two. 5. RL = Load resistance. 6. RE = Emitter resistance between Pins 2 and 3. 7. re = Transistor dynamic emitter resistance, at 25°C; re 26 mV I5 (mA) 8. K = Boltzmann′s Constant, T = temperature in degrees Kelvin, q = the charge on an electron. The gain from the modulating signal input port to the output is the MC1496 gain parameter which is most often of interest to the designer. This gain has significance only when the lower differential amplifier is operated in a linear mode, but this includes most applications of the device. As previously mentioned, the upper quad differential amplifier may be operated either in a linear or a saturated mode. Approximate gain expressions have been developed for the MC1496 for a low−level modulating signal input and the following carrier input conditions: 1) Low−level dc 2) High−level dc 3) Low−level ac 4) High−level ac These gains are summarized in Table 1, along with the frequency components contained in the output signal. APPLICATIONS INFORMATION Double sideband suppressed carrier modulation is the basic application of the MC1496. The suggested circuit for this application is shown on the front page of this data sheet. In some applications, it may be necessary to operate the MC1496 with a single dc supply voltage instead of dual supplies. Figure 25 shows a balanced modulator designed for operation with a single 12 Vdc supply. Performance of this circuit is similar to that of the dual supply modulator. AM Modulator The circuit shown in Figure 26 may be used as an amplitude modulator with a minor modification. All that is required to shift from suppressed carrier to AM operation is to adjust the carrier null potentiometer for the proper amount of carrier insertion in the output signal. However, the suppressed carrier null circuitry as shown in Figure 26 does not have sufficient adjustment range. Therefore, the modulator may be modified for AM operation by changing two resistor values in the null circuit as shown in Figure 27. Product Detector The MC1496 makes an excellent SSB product detector (see Figure 28). This product detector has a sensitivity of 3.0 V and a dynamic range of 90 dB when operating at an intermediate frequency of 9.0 MHz. The detector is broadband for the entire high frequency range. For operation at very low intermediate frequencies down to 50 kHz the 0.1 F capacitors on Pins 8 and 10 should be increased to 1.0 F. Also, the output filter at Pin 12 can be tailored to a specific intermediate frequency and audio amplifier input impedance. As in all applications of the MC1496, the emitter resistance between Pins 2 and 3 may be increased or decreased to adjust circuit gain, sensitivity, and dynamic range. This circuit may also be used as an AM detector by introducing carrier signal at the carrier input and an AM signal at the SSB input. The carrier signal may be derived from the intermediate frequency signal or generated locally. The carrier signal may
Mc1496,Mc1496B be introduced with or without modulation, provided its level Figures 30 and 3 1 show a broadband frequency doubler is sufficiently high to saturate the upper quad differential and a tuned output very high frequency (VHF) doubler, amplifier. If the carrier signal is modulated, a 300 mVrms respectively input level is recommended Phase detection and fm detection Doubly Balanced Mixer The MC1496 will function as a phase detector. High-level The MC1496 may be used as a doubly balanced mixer input signals are introduced at both inputs. When both inputs ith either broadband or tuned narrow band input and output are at the same frequency the MC1496 will deliver an output which is a function of the phase difference between the two The local oscillator signal is introduced at the carrier input input signals. port with a recommended amplitude of 100 m Vrms An FM detector may be constructed by using the phase Figure 29 shows a mixer with a broadband input and a detector principle. A tuned circuit is added at one of the tuned output inputs to cause the two input signals to vary in phase as a The MC1496 will operate as a frequency doubler by output which is a function of the input signal frequeney.an function of frequency. The MC1496 will then provide Frequency Doubler ntroducing the same frequency at both input port TYPICAL APPLICATIONS 12 Vdc 0.1uF 10k5。30 25F Mc1496 Carrier● ignal Input 14 10k>10k 5>68k Figure 25. Balanced Modulator Figure 26. Balanced Modulator-Demodulator (12 Vdc Single Supply) 312 Vdc 13k uF 29 Re 1.0k 10k 00 30k +o Carrier Input 0.uF Mc1496 Input vs 300 mVrms Mc1496 Figure 27 AM Modulator circuit Figure 28. Product Detector (12 Vdc Single Supply) httpllonsemi.com
MC1496, MC1496B http://onsemi.com 10 be introduced with or without modulation, provided its level is sufficiently high to saturate the upper quad differential amplifier. If the carrier signal is modulated, a 300 mVrms input level is recommended. Doubly Balanced Mixer The MC1496 may be used as a doubly balanced mixer with either broadband or tuned narrow band input and output networks. The local oscillator signal is introduced at the carrier input port with a recommended amplitude of 100 mVrms. Figure 29 shows a mixer with a broadband input and a tuned output. Frequency Doubler The MC1496 will operate as a frequency doubler by introducing the same frequency at both input ports. Figures 30 and 31 show a broadband frequency doubler and a tuned output very high frequency (VHF) doubler, respectively. Phase Detection and FM Detection The MC1496 will function as a phase detector. High−level input signals are introduced at both inputs. When both inputs are at the same frequency the MC1496 will deliver an output which is a function of the phase difference between the two input signals. An FM detector may be constructed by using the phase detector principle. A tuned circuit is added at one of the inputs to cause the two input signals to vary in phase as a function of frequency. The MC1496 will then provide an output which is a function of the input signal frequency. VS DSB MC1496 VCC 12 Vd − R1 + Carrier Input 60 mVrms Carrier Input 1.0 k 1.0 k Carrier Null Carrier Adjust 1.0 k Re 1.0 k 2 RL 3 3.9 k RL 3.9 − + 12 6 I5 6.8 k VEE −8.0 Vdc 10 k 51 51 10 k Modulating Signal Input VC 14 5 0.1 F 0.1 F 50 k + − MC1496 Output 0.1 F 0.1 F 0.1 F VCC 12 Vdc 10 k 100 100 10 k 3.0 k 3.0 k 1.0 k 820 1.3 k 50 k 10 k 10 F 15 V Signal Input 300 mVrms Modulating Carrier Null + 25 F 15 V 51 25 F 15 V 2 3 14 5 Modulating Signal Input VS VC 1.0 F Carrier Input 50 k 750 750 51 51 VEE −8.0 Vdc 15 6.8 k RL 3.9 k Re 1.0 k 2 3 14 5 0.1 F −Vo +Vo VCC 12 Vdc 51 51 1.0 k 1.0 k MC1496 2 3 14 5 MC1496 820 1.3 k 1.0 k Carrier Input 300 mVrms SSB Input 51 100 3.0 k 3.0 k 0.005 F 10 k 0.1 F 1.0 k 0.1 F 0.1 F 0.1 F 0.1 F VCC 12 Vdc AF Outp RL 10 0.005 F TYPICAL APPLICATIONS 1.0 k 8 4 1 10 12 6 12 6 12 6 RL 3.9 k 8 4 1 10 8 4 1 10 8 4 1 10 Figure 25. Balanced Modulator (12 Vdc Single Supply) Figure 26. Balanced Modulator−Demodulator Figure 27. AM Modulator Circuit Figure 28. Product Detector (12 Vdc Single Supply) 1.0 k 0.005 F
