查询LF353供应商 National December 2003 Semiconductor LF353 三 Wide Bandwidth Dual JFET Input Operational Amplifier 0 General Description Features These devices are low cost, high speed, dual JFET input Internally trimmed offset voltag operational amplifiers with an internally trimmed input offset Low input bias current voltage(Bl-FET Il technology). They require low supply Low input noise voltage 25 nV/Hz 0.01 pA/vHz slew rate. In addition, well matched high voltage JFET input a Wide gain bandwidth 4 MHZ devices provide very low input bias and offset currents. The High slew rate 13 V/H designers to immediately upgrade the overall performance of w supply current: xisting LM1558 and 8 designs ■ High input impedance fiers may ≤0.02% speed integrators, fast D/A converters, sample and hold Low 1/t noise corner: circuits and many other circuits requiring low input offset Fast settling time to o.01% voltage, low input bias current, high input impedance, high slew rate and wide bandwidth. The devices also exhibit low noise and offset voltage drift. Typical Connection Connection Diagram Dual-n-Line Package UTPUT A INVERTING INPUT A OUTPUT B NON-INVERTING Top View Order Number LF353M. LF353MX or LF353N Simplified schematic See NS Package Number MOBA or NO8E 1/2 Dual ITERNALLY TAIMMED 0064916 BH-FET ll" is a trademark of National Semiconductor Corporation. @2003 National Semiconductor Corporation DS005649 www.nationalcom
LF353 Wide Bandwidth Dual JFET Input Operational Amplifier General Description These devices are low cost, high speed, dual JFET input operational amplifiers with an internally trimmed input offset voltage (BI-FET II™ technology). They require low supply current yet maintain a large gain bandwidth product and fast slew rate. In addition, well matched high voltage JFET input devices provide very low input bias and offset currents. The LF353 is pin compatible with the standard LM1558 allowing designers to immediately upgrade the overall performance of existing LM1558 and LM358 designs. These amplifiers may be used in applications such as high speed integrators, fast D/A converters, sample and hold circuits and many other circuits requiring low input offset voltage, low input bias current, high input impedance, high slew rate and wide bandwidth. The devices also exhibit low noise and offset voltage drift. Features n Internally trimmed offset voltage: 10 mV n Low input bias current: 50pA n Low input noise voltage: 25 nV/√Hz n Low input noise current: 0.01 pA/√Hz n Wide gain bandwidth: 4 MHz n High slew rate: 13 V/µs n Low supply current: 3.6 mA n High input impedance: 1012Ω n Low total harmonic distortion : ≤0.02% n Low 1/f noise corner: 50 Hz n Fast settling time to 0.01%: 2 µs Typical Connection 00564914 Simplified Schematic 1/2 Dual 00564916 Connection Diagram Dual-In-Line Package 00564917 Top View Order Number LF353M, LF353MX or LF353N See NS Package Number M08A or N08E BI-FET II™ is a trademark of National Semiconductor Corporation. December 2003 LF353 Wide Bandwidth Dual JFET Input Operational Amplifier © 2003 National Semiconductor Corporation DS005649 www.national.com 查询LF353供应商
4/ Absolute Maximum Ratings(Note 1) Small Outline Package If Military/Aerospace specified devices are required Vapor Phase(60 sec.) 215"c please contact the National Semiconductor Sales Office/ Infrared (15 se 220c Distributors for availability and specifications. See AN-450"Surface Mounting Methods and Their Effect ±18V on Product Reliability for other methods of soldering (Note 2 surface mount devices Operating Temperature Range o°cto+70'C ESD Tolerance( Note 8) 150°C HJA M Package Differential Input Voltage Note 1: mum Ratings indicate limits beyond which damage Input Voltage Range( Note 3) Output Short Circuit Duration ite DC and AC electrcal specifications under part Storage Temperature Range -65cto+150C Lead Temp. (Soldering, 10 sec. ting Ratings. Specifications are not guar- anteed for parameters where no limit is given, however, the typical value is a dering Information good indication of device performance. Dual-In-Line Package Soldering(10 sec. 260c DC Electrical Characteristics (Note 5) Parameter Conditions LF353 yp Input Offset Voltage Rs=10KQ,TA=25'C 5 Over Temperature 13 △Vos△T| Average TC of Input Offset Voltage s=10k2 T=25 C,(Notes 5, 6) T≤70c Input Bias Current =25c,( Notes5,6) T≤70c 8 DA Large Signal Voltage Gain vs=±15V,TA=250 Vo=±10V,RL=2k Over Temperature Output Voltage Swing Vs=±15v,R1=10k ±12±135 Input Common-Mode Voltage Vs=±15V 15 CMRRCommon-Mode Rejection Ratio Rs≤10kg 70 100 PSRR Supply Voltage Rejection Ratio (Note 7) 0 Supply Current AC Electrical Characteristics Symbol Parameter LF353 Units Max Amplifier to Amplifier Coupling TA=25℃,f=1Hz-20kHz (Input Referred) s=±15V,TA=25C h Pr =25 Equivalent Input Noise Voltage TA=25C,Rs=1009 nv/、Hz f=1000Hz Equivalent Input Noise Current T=25C,f=1000Hz 0.01 www.national.com
Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ±18V Power Dissipation (Note 2) Operating Temperature Range 0˚C to +70˚C Tj (MAX) 150˚C Differential Input Voltage ±30V Input Voltage Range (Note 3) ±15V Output Short Circuit Duration Continuous Storage Temperature Range −65˚C to +150˚C Lead Temp. (Soldering, 10 sec.) 260˚C Soldering Information Dual-In-Line Package Soldering (10 sec.) 260˚C Small Outline Package Vapor Phase (60 sec.) 215˚C Infrared (15 sec.) 220˚C See AN-450 “Surface Mounting Methods and Their Effect on Product Reliability” for other methods of soldering surface mount devices. ESD Tolerance (Note 8) 1000V θJA M Package TBD Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which guarantee specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not guaranteed for parameters where no limit is given, however, the typical value is a good indication of device performance. DC Electrical Characteristics (Note 5) Symbol Parameter Conditions LF353 Units MIn Typ Max VOS Input Offset Voltage RS=10kΩ, TA=25˚C 5 10 mV Over Temperature 13 mV ∆VOS/∆T Average TC of Input Offset Voltage RS=10 kΩ 10 µV/˚C IOS Input Offset Current Tj =25˚C, (Notes 5, 6) 25 100 pA Tj ≤70˚C 4 nA IB Input Bias Current Tj =25˚C, (Notes 5, 6) 50 200 pA Tj ≤70˚C 8 nA RIN Input Resistance Tj =25˚C 1012 Ω AVOL Large Signal Voltage Gain VS=±15V, TA=25˚C 25 100 V/mV VO=±10V, RL=2 kΩ Over Temperature 15 V/mV VO Output Voltage Swing VS=±15V, RL=10kΩ ±12 ±13.5 V VCM Input Common-Mode Voltage VS=±15V ±11 +15 V Range −12 V CMRR Common-Mode Rejection Ratio RS≤ 10kΩ 70 100 dB PSRR Supply Voltage Rejection Ratio (Note 7) 70 100 dB IS Supply Current 3.6 6.5 mA AC Electrical Characteristics (Note 5) Symbol Parameter Conditions LF353 Units Min Typ Max Amplifier to Amplifier Coupling TA=25˚C, f=1 Hz−20 kHz −120 dB (Input Referred) SR Slew Rate VS=±15V, TA=25˚C 8.0 13 V/µs GBW Gain Bandwidth Product VS=±15V, TA=25˚C 2.7 4 MHz en Equivalent Input Noise Voltage TA=25˚C, RS=100Ω, 16 f=1000 Hz in Equivalent Input Noise Current Tj =25˚C, f=1000 Hz 0.01 LF353 www.national.com 2
AC Electrical Characteristics ( Continued) (Note 5) Symbol Conditions LF353 MinTypMax THD Total Harmonic Distortion Av=+10,RL=10k <0.02 BW=20 Hz-20 kHz ed temperatures, the device must be derated based on a thermal resistance of 115 C/ typ junction to ambient for the N package. and 158 C/ typ junction to ambient for the H package. Note 3: Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage. Note 4: The power dissipation limit, however, can production test time, the input bias currents measured are correlated to junction temperature. In normal operation the junction temperature rises above the an emperature as a result of intemal power dissipation, PD- TFTA+A PD where BA is the thermal resistance from junction to ambient. Use of a heat sink is recommended if input bias current is to be kept to a minimum ote 7: Supply voltage rejection ratio is measured for both supply magnitudes increasing or decreasing simultaneously in accordance with common practice. vs =±6Vto±15V Note 8: Human body model, 1.5 k]2 in series with 100 pF. Typical Performance Characteristics Input Bias Current Input Bias Current 80 COMMON-MODE VOLTAGE (V) TEMPERATURE C) Supply Current Positive Common-Mode Input Voltage Limit 0°≤TA≤+70° c≤TA≤+70 28 POSITIVE SUPPLY VOLTAGE (V) SUPPLY VOLTAGE(±v)
AC Electrical Characteristics (Continued) (Note 5) Symbol Parameter Conditions LF353 Units Min Typ Max THD Total Harmonic Distortion AV=+10, RL=10k, VO=20Vp−p, BW=20 Hz-20 kHz <0.02 % Note 2: For operating at elevated temperatures, the device must be derated based on a thermal resistance of 115˚C/W typ junction to ambient for the N package, and 158˚C/W typ junction to ambient for the H package. Note 3: Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage. Note 4: The power dissipation limit, however, cannot be exceeded. Note 5: These specifications apply for VS=±15V and 0˚C≤TA≤+70˚C. VOS, IBand IOS are measured at VCM=0. Note 6: The input bias currents are junction leakage currents which approximately double for every 10˚C increase in the junction temperature, Tj . Due to the limited production test time, the input bias currents measured are correlated to junction temperature. In normal operation the junction temperature rises above the ambient temperature as a result of internal power dissipation, PD. Tj =TA+θjA PD where θjA is the thermal resistance from junction to ambient. Use of a heat sink is recommended if input bias current is to be kept to a minimum. Note 7: Supply voltage rejection ratio is measured for both supply magnitudes increasing or decreasing simultaneously in accordance with common practice. VS = ±6V to ±15V. Note 8: Human body model, 1.5 kΩ in series with 100 pF. Typical Performance Characteristics Input Bias Current Input Bias Current 00564918 00564919 Supply Current Positive Common-Mode Input Voltage Limit 00564920 00564921 LF353 3 www.national.com
E Typical Performance Characteristics (Continued) Negative Common-Mode Input Voltage Limit Positive current limit 0c≤TA≤+70 三 u2ouz 9 3=au>a NEGATIVE SUPPLY VOLTAGE (V) OUTPUT SOURCE CURRENT (mA) Negative Current Limit Voltage Swing -15 2>u2z TA="C 2=9 OUTPUT SINK CURRENT (mA) SUPPLY VOLTAGE (+V) s64925 Output Voltage Swing Gain Bandwidth TA= 25C 45 2是> CL-100 pF 0203040506070 RL-OUTPUT LOAD (ks2 TEMPERATURE (C) cs64927 www.national.com
Typical Performance Characteristics (Continued) Negative Common-Mode Input Voltage Limit Positive Current Limit 00564922 00564923 Negative Current Limit Voltage Swing 00564924 00564925 Output Voltage Swing Gain Bandwidth 00564926 00564927 LF353 www.national.com 4
Typical Performance Characteristics (Continued) Bode plot Slew Rate PHASE 0京 RISING FREQUENCY(MHz) TEMPERATURE ( C) Distortion vS Frequency Undistorted Output Voltage Swing 0175TA=5c Vo=20 V Av=100 0.075 >3 FREQUENCY(Hz) FREQUENCY(H Open Loop Frequency Response Common-Mode Rejection Ratio 它100 TA=25°C +OPEN LOOP 当20 VOLTAGE GAIN 101001k10k100k1M10M 101001k10k100k1M10M FREQUENCY(Hz) FREQUENCY(Hz) 5
Typical Performance Characteristics (Continued) Bode Plot Slew Rate 00564928 00564929 Distortion vs. Frequency Undistorted Output Voltage Swing 00564930 00564931 Open Loop Frequency Response Common-Mode Rejection Ratio 00564932 00564933 LF353 5 www.national.com
E Typical Performance Characteristics (Continued) Power Supply Rejection Ratio Equivalent Input Noise Voltage TA-25 c E>∽ +SUPPLY 2与 SUPPLY 101001K10k100k1M10M 1001k 10k100k FREQUENCY(Hz FREQUENCY(Hz) 00564935 Open Loop Voltage Gain(VM) Output Impedance A=0cT0+25°c TA-25C Av=100 >2 0.01 SUPPLY VOLTAGE(tV) REQUENCY(Hz) Inverter Settling Time 2至秀 TA-25c ETTLING TIME (us) www.national.com
Typical Performance Characteristics (Continued) Power Supply Rejection Ratio Equivalent Input Noise Voltage 00564934 00564935 Open Loop Voltage Gain (V/V) Output Impedance 00564936 00564937 Inverter Settling Time 00564938 LF353 www.national.com 6
Pulse Response Small Signal Non-Inverting Small Signaling Inverting s>E≌二 是=H TIME (0.2 us/DIV TIME(0. 2 us/DIV) 00564905 Large Signal Inverting 2295 TIME (2 us/DIV 0554907 Current Limit(RL= 10022 zHP> Application Hints These devices are op amps with an intemally trimmed input should be allowed to exceed the negative supply as this will offset voltage and JFET input devices(BI-FET Ii).These source and drain eliminating the need for clamps across the ding the negative common-mode limit on either input rce the output to a high state, potentially causing a inputs. Therefore, large differential input voltages can easily reversal of phase to the output. Exceeding the negative be accommodated without a large increase in input current. The maximum differential input voltage is independent of the common-mode limit on both inputs will force the amplifier output to a high state. In neither case does a latch occur
Pulse Response Small Signaling Inverting 00564904 Large Signal Inverting 00564906 Small Signal Non-Inverting 00564905 Large Signal Non-Inverting 00564907 Current Limit (RL = 100Ω) 00564908 Application Hints These devices are op amps with an internally trimmed input offset voltage and JFET input devices (BI-FET II). These JFETs have large reverse breakdown voltages from gate to source and drain eliminating the need for clamps across the inputs. Therefore, large differential input voltages can easily be accommodated without a large increase in input current. The maximum differential input voltage is independent of the supply voltages. However, neither of the input voltages should be allowed to exceed the negative supply as this will cause large currents to flow which can result in a destroyed unit. Exceeding the negative common-mode limit on either input will force the output to a high state, potentially causing a reversal of phase to the output. Exceeding the negative common-mode limit on both inputs will force the amplifier output to a high state. In neither case does a latch occur LF353 7 www.national.com
4/ Application Hints (Continued) or that the unit is not inadvertently installed backwards in a socket as an unlimited current surge through the resulting since raising the input back within the common-mode range forward diode within the IC could cause fusing of the intemal gain puts the input stage and thus the amplifier in a normal conductors and result in a destroyed unit. operating mode As with most amplifiers, care should be taken with lead Exceeding the positive common-mode limit on a single input dress, component placement and supply decoupling in order will not change the phase of the output; however, if both to ensure stability. For example, resistors from the output to inputs exceed the limit, the output of the amplifier will be an input should be placed with the body close to the input to forced to a high state minimize "pick-up" and maximize the frequency of the feed- The amplifiers will operate with a common-mode input volt back pole by minimizing the capacitance from the input to age equal to the positive supply; however, the gain band ground. width and slew rate may be decreased in this condition. A feedback pole is created when the feedback around any When the negative common-mode voltage swings to within amplifier is resistive. The parallel resistance and capacitance 3V of the negative supply, an increase in input offset voltage from the input of the device(usually the inverting input) to AC ground set the frequency of the pole. In many instances the Each amplifier is individually biased by a zener reference frequency of this pole is much greater than the expected 3 which allows normal circuit operation on +6V power sup dB frequency of the closed loop gain and consequently there plies. Supply voltages less than these may result in lower is negligible effect on stability margin. However, if the feed- gain bandwidth and slew rate. ack pole is less than approximately 6 times the expected 3 The amplifiers will drive a 2 k2 load resistance to +10V over dB frequency a lead capacitor should be placed from the the full temperature range of oC to +70'C. If the amplifier is output to the input of the op amp. The value of the added forced to drive heavier load currents however. an increase apacitor should be such that the Rc time constant of this in input offset voltage may occur on the negative voltage apacitor and the resistance it parallels is greater than or wing and finally reach an active current limit on both posi- equal to the original feedback pole time constant tive and negative swings Precautions should be taken to ensure that the power supp for the integrated circuit never becomes reversed in polarity Detailed schematic D2 EE www.national.com
Application Hints (Continued) since raising the input back within the common-mode range again puts the input stage and thus the amplifier in a normal operating mode. Exceeding the positive common-mode limit on a single input will not change the phase of the output; however, if both inputs exceed the limit, the output of the amplifier will be forced to a high state. The amplifiers will operate with a common-mode input voltage equal to the positive supply; however, the gain bandwidth and slew rate may be decreased in this condition. When the negative common-mode voltage swings to within 3V of the negative supply, an increase in input offset voltage may occur. Each amplifier is individually biased by a zener reference which allows normal circuit operation on ±6V power supplies. Supply voltages less than these may result in lower gain bandwidth and slew rate. The amplifiers will drivea2kΩ load resistance to ±10V over the full temperature range of 0˚C to +70˚C. If the amplifier is forced to drive heavier load currents, however, an increase in input offset voltage may occur on the negative voltage swing and finally reach an active current limit on both positive and negative swings. Precautions should be taken to ensure that the power supply for the integrated circuit never becomes reversed in polarity or that the unit is not inadvertently installed backwards in a socket as an unlimited current surge through the resulting forward diode within the IC could cause fusing of the internal conductors and result in a destroyed unit. As with most amplifiers, care should be taken with lead dress, component placement and supply decoupling in order to ensure stability. For example, resistors from the output to an input should be placed with the body close to the input to minimize “pick-up” and maximize the frequency of the feedback pole by minimizing the capacitance from the input to ground. A feedback pole is created when the feedback around any amplifier is resistive. The parallel resistance and capacitance from the input of the device (usually the inverting input) to AC ground set the frequency of the pole. In many instances the frequency of this pole is much greater than the expected 3 dB frequency of the closed loop gain and consequently there is negligible effect on stability margin. However, if the feedback pole is less than approximately 6 times the expected 3 dB frequency a lead capacitor should be placed from the output to the input of the op amp. The value of the added capacitor should be such that the RC time constant of this capacitor and the resistance it parallels is greater than or equal to the original feedback pole time constant. Detailed Schematic 00564909 LF353 www.national.com 8
Typical Applications Three-Band Active Tone Control B00sT…cUT 022 1/2LF353 AOoUT REQUENCY《Hz) Note 1: All controls flat Note 2: Bass and treble boost, mid fat. Note 3: Bass and treble cut. mid flat. Note 4: Mid boost, bass and treble flat. Note 5: Mid cut, bass and treble flat. All potentiometers are linear taper Use the LF347 Quad for stereo application
Typical Applications Three-Band Active Tone Control 00564939 00564940 Note 1: All controls flat. Note 2: Bass and treble boost, mid flat. Note 3: Bass and treble cut, mid flat. Note 4: Mid boost, bass and treble flat. Note 5: Mid cut, bass and treble flat. • All potentiometers are linear taper • Use the LF347 Quad for stereo applications LF353 9 www.national.com
Typical Applications Improved CMRR Instrumentation Amplifier SEPARATE 力and吉 are separate isolated grounds 1400, resistor matching =0.01%: CMRR- 136 dB Fourth order Low pass Butterworth Filter 工 www.national.com
Typical Applications (Continued) Improved CMRR Instrumentation Amplifier 00564941 Fourth Order Low Pass Butterworth Filter 00564942 LF353 www.national.com 10
