K科拉 EDA技术与VHDL 第4章 Qiartus IⅡ使用方法
EDA技术与VHDL 第4章 Qiartus II 使用方法 KX 康芯科技
K 康芯科技 4.1 Quartusll-设计流程 1.创建工程准备工作 9 QuartusⅡ File Edit View P New Device Design Files Software Files Other Files Entity AH四L File Block Diagram/Schematic File △Compilation EDIF File Verilog HDL File VHDL File △間的 Module Pr 图4-1选择编辑文件
KX 康芯科技 4.1 QuartusII设计流程 1．创建工程准备工作 图4-1 选择编辑文件 KONXIN
K康科技 4.1 Quartusll设计流程 1.创建工程准备工作 的 abe Vhdl1.vhd* 1 LIBRARY IEEE: 2 USE IEEE.STD LOGIC 1164.ALL; 石 3 USE IEEE.STD LOGIC UNSIGNED.ALL: ENTITY CNT10 IS 享 PORT (CLK,RST,EN:IN STD LOGIC; 享 6 7 COUT:OUT Save As 8 END CNT10: % 9 ARCHITECTURI 保存在)： 合CXT1OB 包酽国 10 BEGIN 11 PROCESS 昌 12 VARIAB Quartus II 我最近的文档 13 BEGIN 14 IF RS 15 A Do you want to create a new project with this file? ELSI 16 IF 桌面 是 否) 取消 18 图4-2选择编辑文件的语言类型，键入源程序并存盘
KX 康芯科技 4.1 QuartusII设计流程 1．创建工程准备工作 图4-2 选择编辑文件的语言类型，键入源程序并存盘
K蘖还科技 4.1 Quartusll-设计流程 2.创建工程 Nev Project Vizard:Directory,Nane,Top-Level Entity [pag. What is the working directory for this project? D:\CNT10B What is the name of this project? CNT10 What is the name of the top-level design entity for this project?This name is case sensitive and must exactly match the entity name in the design file. CNT10 Use Existing Project Settings. 图4-3利用“New Preject Wizard"创建工程cnt10
KX 康芯科技 4.1 QuartusII设计流程 2. 创建工程 图4-3 利用“New Preject Wizard”创建工程cnt10
K康心科技 4.1 Quartusll-设计流程 2.创建工程 Nev Project Vizard:Add Files [page 2 of 5] 为 Select the design files you want to include in the project.Click Add All to add all design files in the project directory to the project.Note:you can always add design files to the project later. Eile name: △dd File name Type AddA CNT10.vhd VHDL File Remove 图4-4将所有相关的文件都加入进此工程
KX 康芯科技 4.1 QuartusII设计流程 2.创建工程 图4-4 将所有相关的文件都加入进此工程
K康芯科技 4.1 Quartusll-设计流程 2.创建工程 Nev Project Wizard:Family Device Settings [page 3 of 5] Select the family and device you want to target for compilation. Show in Available device'list Eamily: Cyclone Package: POFP -Target device CAuto device selected by the Fitter Pin count: 240 Specific device selected in 'Available devices'list Speed grade: 8 Core voltage: 1.5/ Show Advanced Devices Available devices: Name LEs Memor.PLL EP1C60240C8 5980 92160 2 EP1C120240C8 12060 239616 2 图4-5选择目标器件EP1C6Q240C8
KX 康芯科技 4.1 QuartusII设计流程 2.创建工程 图4-5 选择目标器件EP1C6Q240C8
K能芯科技 4.1 Quartusll-设计流程 3.编译前设置 Device Pin Options Dual-Purpose Pins Voltage Pin Placement Error Detection CRC General Configuration Programming Files Unused Pins Specify general device options.These options are not dependent on the configuration scheme. ☐ptions: Auto-restart configuration after error Release clears before tri-states Enable user-supplied start-up clock [CLKUSR] Enable device-wide reset (DEV_CLRn) Enable device-wide output enable (DEV_OE) Enable INIT_DONE output □Auto usercode JTAG user code (32-bit hexadecimal): ED32567 图4-6选择配置器件的工作方式
KX 康芯科技 4.1 QuartusII设计流程 3．编译前设置 图4-6 选择配置器件的工作方式
K康芯科技 4.1 Quartusll-设计流程 3.编译前设置 Device Pin Options Dual-Purpose Pins Voltage Pin Placement Error Detection CRC General Configuration Programming Files Unused Pins Specify the device configuration scheme and the configuration device. Configuration scheme:Active Serial (can use Configuration Device] Configuration mode: Standard Configuration device Use configuration device: EPCS1 Configuration Device Options Generate compressed bitstreams 图4-7选择配置器件和编程方式
KX 康芯科技 4.1 QuartusII设计流程 3．编译前设置 图4-7 选择配置器件和编程方式
4.全程编译 K康恋科技 Quartus II -D:/CNT10B/CNT10 -CNT10 [Compilation Report Flow Sumsary] ⑨1 e Edit Viee Projeet Assignments Processing Tools Window Help ·它日曼%陷色 2CNT10 效’g必等>6⑨少迎 Project Navigator b CNT10.vhd Compilation Report-Flow Summary Entity Logic Cyelone:EP1C6Q240C8 Compilation Report Flow Summary 鸟凸Legal Notice -◆C2T10 鸟里1 ow Summary low Settings 日 用Flow Non-Default G 里1ow1 apsed Time Flow Status Flow Failed -Tue Aug 01 18:28 △Hierarchy目FilesDesign Units 哥目1 Ow Log Quartus II Version 6.0Bui1d17804/27/2006SJFy 田☐Analysis&Synthesi Status ✉x Revision Name CNT10 周ole Top-level Entity Name CNT10 Full Compilation Family 12% Cyclone Analysis Synthesis Device EP1C6Q240C8 49% Final Fitter 0% Timing Models Met timing requirements N/A -Assembler 0% Timing Analyzer 0% Quartus II 函 Full Compilation was NOT successful (3 errors) Inf0:木木木本方吉者市木*方方者吉本本木本者古 确定门 Info:Running Quartus II Info:Command:quartus_map -read_settings_files=on -vrite_settings_files=off CNT10-c CNT10 Ertor (10500):VHDL syntax error at CNT10.vhd(9)near text "ARCHITECTURE";expecting "; Error (10396):VHDL syntax error at CNT10.vhd(27):name used in construct must match previously specified name Error (105231:Tmored construct.CNTI0 at.CNTI0.vhd/41 due to nrevious errors 图4-8全程编译后出现报错信息
KX 康芯科技 图4-8 全程编译后出现报错信息 4．全程编译
K康芯科技 4.1 Quartusll-设计流程 5.时序仿真 Nev ☒ Device Design Files Other Files AHDL Include File Block Symbol File Chain Description File Hexadecimal (Intel-Format]File Logic Analyzer Interface File Memory Initialization File SignalT ap ll File Tcl Script File Text File Vector Waveform File 图4-9选择编辑矢量波形文件
KX 康芯科技 4.1 QuartusII设计流程 图4-9 选择编辑矢量波形文件 5．时序仿真