复旦大学：《集成电路工程》教学资源（硕士士学位论文）分数分频频率综合器中噪声折叠问题的研究与电路设计.pdf_大学文库

I 目录图目录····························································································III 表目录·····························································································V 摘要······························································································VII Abstract ······················································································VIII 第一章绪论 ···················································································VII 1.1 研究背景··············································································1 1.2 论文主要贡献········································································2 1.3 论文的研究内容和组织结构······················································2 第二章锁相环型频率综合器概述··························································5 2.1 引言····················································································5 2.2 整数分频频率综合器的基本结构················································5 2.3 整数分频频率综合器的基本结构················································6 2.3.1 累加器型分数分频频率综合器 ··········································6 2.3.2 ΣΔ 分数分频频率综合器 ··················································8 2.4 重要参数·············································································10 2.4.1 杂散和相位噪声的定义 ··················································10 2.4.2 相位噪声模型 ······························································12 2.4.3 参考杂散 ····································································15 2.4.4 分数杂散 ····································································21 2.5 本章小结·············································································24 第三章分数分频频率综合器非线性分析················································25 3.1 引言···················································································25 3.2 ΣΔ 分数分频频率综合器的基本结构及噪声模型 ···························25 3.2.1 基本结构 ····································································25 3.2.2 量化噪声与 ΣΔ 调制器结构·············································26 3.2.3 非线性条件下的噪声模型 ···············································29 3.3 本章小结·············································································37 第四章电路设计··············································································39 4.1 引言···················································································39 4.2 线性鉴频鉴相器电路设计························································39 4.2.1 鉴频鉴相器和电荷泵的传输特性······································40

II 4.2.2 现有的线性化技术介绍 ··················································41 4.2.3 线性鉴频鉴相器电路设计 ···············································43 4.3 分频器链设计·······································································47 4.4 分数杂散的设计考虑······························································49 4.5 本章小结·············································································49 第五章芯片设计及芯片测试·······························································51 5.1 引言···················································································51 5.2 芯片实现·············································································51 5.3 测试结果·············································································53 5.3.1 频率调谐范围最小分辨率及功耗测试结果··························53 5.3.2 相位噪声测试结果 ························································53 5.3.3 分数杂散测试结果 ························································55 5.3.4 环路带宽和积分相位误差测试结果···································56 5.3.5 分频器链性能测试结果 ··················································57 5.3.6 锁定时间测试结果 ························································59 5.4 本章小结·············································································60 第六章总结与展望···········································································61 6.1 工作总结·············································································61 6.2 未来展望·············································································62 参考文献·························································································63 致谢·······························································································67

III 图目录图 2-1 整数分频频率综合器结构框图..............................................................5 图 2-2 基于累加器的分数分频频率综合器结构框图.........................................7 图 2-3 分频比在 4.25 时分数分频频率综合器中的量化噪声 ............................7 图 2-4 ΣΔ 分数分频综合器结构框图 ................................................................8 图 2-5 ΣΔ 型频率综合器噪声特性....................................................................9 图 2-6 正弦信号的频谱 .................................................................................10 图 2-7 毛刺和相位噪声 .................................................................................12 图 2-8 整数分频频率综合器的 s 域模型 ........................................................13 图 2-9 整数分频频率综合器相位噪声模型.....................................................13 图 2-10 各模块自身噪声、噪声传递函数和等效输出噪声 .............................15 图 2-11 理想情况下整数分频综合器工作状态................................................16 图 2-12 泄漏电流引起参考杂散的机制..........................................................18 图 2-13 控制信号 up 和 dn 的偏差对参考杂散的影响....................................19 图 2-14 延迟平衡的鉴频鉴相器.....................................................................19 图 2-15 电荷泵失配对参考杂散的影响..........................................................20 图 2-16 电荷共享对参考杂散的影响..............................................................21 图 2-17 产生分数杂散的三种耦合机制..........................................................22 图 2-18 周期矩形波信号 ...............................................................................23 图 3-1 基于 ΣΔ 调制器的分数分频频率综合器的结构....................................26 图 3-2 一阶 ΣΔ 调制器结构及线性化 z 域模型 ..............................................27 图 3-3 分数分频频率综合器噪声模型............................................................28 图 3-4 分数分频器参考时钟和分频器时钟工作状态.......................................29 图 3-5 电荷泵模型.........................................................................................31 图 3-6 电荷泵数学模型 .................................................................................32 图 3-7 存在非线性情况下分数分频频率综合器噪声模型 ...............................33 图 3-8 存在非线性情况下量化噪声对输出噪声的贡献...................................36 图 4-1 PFD/CP 结构及理想 CP 情况下传输特性............................................40 图 4-2 PFD/CP 的非线性情况下的传输曲线 ..................................................40 图 4-3 dc Current Offset 线性化技术 .............................................................41 图 4-4 增加延时来消除非线性的电路结构及工作时序图 ...............................42 图 4-5 基于采样开关的环路滤波器................................................................43

摘要数字电视标准多样性、下一代数字电视标准以及人们对于高清电视转播的需求，给射频接收机关键模块之一的频率综合器的设计带来了诸多挑战。如何获得宽的频率调谐范围及低的相位噪声性能是频率综合器设计的难点。而在电荷泵型频率综合器中，存在着噪声折叠问题，使其难以获得低的相位噪声性能。本文主要围绕解决噪声折叠问题和提高带内相位噪声性能展开工作，在线性化技术、分频器链的设计等方面提出相应的理论分析及相关解决方法，并通过芯片实现及测试来加以验证。论文回顾了电荷泵型频率综合器的基本结构，介绍了分数分频频率综合器的几个关键性能指标。分析了Σ△型分数分频频率综合器的基本结构，确定了∑△调制器的噪声模型。结合∑△调制器量化噪声的模型和频率综合器的噪声模型给出了∑△型分数分频频率综合器噪声模型并分析了调制器量化噪声到环路输出相位噪声的转换过程，重点分析了电路非线性引起的带外量化噪声折叠回带内恶化带内相位噪声的机制。通过对电路非线性以及引起噪声折叠的机制的理论分析，提出了一种线性化的技术，设计了线性鉴频鉴相器(PFD)电路，完全消除了噪声折叠的影响，同时避免恶化参考杂散性能及增加电路设计难度。分析了分频器对于降低相位噪声的作用，设计了分频器链电路，获得了覆盖VHF和UHF波段、低相位噪声的正交本振信号。在前面理论分析及电路设计的基础上，参与设计的频率综合器在TSMC 0.18-um CMOS工艺下实现流片，芯片面积为840μm×970μm,功耗36mW, 带内相位噪声为-107 dBc/Hz,比起有噪声折叠问题的频率综合器，带内相位噪声有大于10dB/Hz的优化。积分相位误差45dB,锁定时间<30μs。关键词：分数分频频率综合器，带内相位噪声，参考杂散，非线性，噪声折叠，线性化技术，线性鉴频鉴相器，分频器链中图分类号：TN4 VII

VII 摘要数字电视标准多样性、下一代数字电视标准以及人们对于高清电视转播的需求，给射频接收机关键模块之一的频率综合器的设计带来了诸多挑战。如何获得宽的频率调谐范围及低的相位噪声性能是频率综合器设计的难点。而在电荷泵型频率综合器中，存在着噪声折叠问题，使其难以获得低的相位噪声性能。本文主要围绕解决噪声折叠问题和提高带内相位噪声性能展开工作，在线性化技术、分频器链的设计等方面提出相应的理论分析及相关解决方法，并通过芯片实现及测试来加以验证。论文回顾了电荷泵型频率综合器的基本结构，介绍了分数分频频率综合器的几个关键性能指标。分析了ΣΔ型分数分频频率综合器的基本结构，确定了ΣΔ调制器的噪声模型。结合ΣΔ调制器量化噪声的模型和频率综合器的噪声模型给出了ΣΔ型分数分频频率综合器噪声模型并分析了调制器量化噪声到环路输出相位噪声的转换过程，重点分析了电路非线性引起的带外量化噪声折叠回带内恶化带内相位噪声的机制。通过对电路非线性以及引起噪声折叠的机制的理论分析，提出了一种线性化的技术，设计了线性鉴频鉴相器(PFD)电路，完全消除了噪声折叠的影响，同时避免恶化参考杂散性能及增加电路设计难度。分析了分频器对于降低相位噪声的作用，设计了分频器链电路，获得了覆盖VHF和UHF波段、低相位噪声的正交本振信号。在前面理论分析及电路设计的基础上，参与设计的频率综合器在TSMC 0.18-μm CMOS工艺下实现流片，芯片面积为840 μm×970 μm，功耗36 mW，带内相位噪声为-107 dBc/Hz，比起有噪声折叠问题的频率综合器，带内相位噪声有大于10 dB/Hz的优化。积分相位误差45 dB，锁定时间<30 μs。关键词：分数分频频率综合器，带内相位噪声，参考杂散，非线性，噪声折叠，线性化技术，线性鉴频鉴相器，分频器链中图分类号：TN4

Abstract There are many different Digital-TV standards around the word,and the next generation standards is published for the delivery of innovative new services like high definition television(HDTV),it brings many challenges for the frequency synthesizer of the RF receivers.The synthesizers must support a wide range frequencies and stringent Phase Noise requirement.However,it is well known that the performance of fractional-N frequency synthesizers is significantly influenced by the circuit nonlinearity.Nonlinearity results in the noise-folding phenomenon,which can seriously degrade the in-band phase noise.This thesis aiming at linearization technique,divider chain and reduction of phase noise especially in-band phase noise. The review of Charge Pump frequency synthesizer and four main fundamental figures of merit is present.The phase noise model of A fractional-N frequency synthesizer is used to analysis the mechanism of noise-folding phenomenon.A detailed theoretical derivation is done to figure out the principle of out-band quantization noise transferring to the in-band phase noise due to the circuit nonlinearity. According to the detailed analysis of the noise-folding phenomenon,a linearization technique is proposed and a modified PFD circuit is designed to solve this problem without raising the reference spurs.A Divider Chain with frequency division by a factor of 2 or its power such as 4/8/16 is realized to extend the frequency coverage,and quadrature I/Q signals with excellent phase noise performance is obtained at same time. Based on the previous theoretical analysis and some techniques,a ZA fractional-N frequency synthesizer was fabricated in a 0.18um CMOS process with a total power consumption of 36mW from a 1.8V supply.The die area is 840umX970um.The in-band phase noise of the synthesizer is-107dBc/Hz at 10kHz offset,the in-band phase noise is more than 10dBc/Hz better than the one with the noise-folding problem.The integrated rms phase error is below 0.6,the worst reference spur is below -74dBc when using the proposed PFD and the worst IRR is 45dB without any calibration and the locking time is less than 30us. Keywords:Fractional-N Frequency Synthesizer,In-band Phase Noise, Reference Spurs,Circuit Nonlinearity,Linear Technique,Noise-folding Phenomenon,Linear PFD,Divider Chain V

VIII Abstract There are many different Digital-TV standards around the word, and the next generation standards is published for the delivery of innovative new services like high definition television (HDTV), it brings many challenges for the frequency synthesizer of the RF receivers. The synthesizers must support a wide range frequencies and stringent Phase Noise requirement. However, it is well known that the performance of fractional-N frequency synthesizers is significantly influenced by the circuit nonlinearity. Nonlinearity results in the noise-folding phenomenon, which can seriously degrade the in-band phase noise. This thesis aiming at linearization technique, divider chain and reduction of phase noise especially in-band phase noise. The review of Charge Pump frequency synthesizer and four main fundamental figures of merit is present. The phase noise model of ΣΔ fractional-N frequency synthesizer is used to analysis the mechanism of noise-folding phenomenon. A detailed theoretical derivation is done to figure out the principle of out-band quantization noise transferring to the in-band phase noise due to the circuit nonlinearity. According to the detailed analysis of the noise-folding phenomenon, a linearization technique is proposed and a modified PFD circuit is designed to solve this problem without raising the reference spurs. A Divider Chain with frequency division by a factor of 2 or its power such as 4/8/16 is realized to extend the frequency coverage, and quadrature I/Q signals with excellent phase noise performance is obtained at same time. Based on the previous theoretical analysis and some techniques, a ΣΔ fractional-N frequency synthesizer was fabricated in a 0.18μm CMOS process with a total power consumption of 36mW from a 1.8V supply. The die area is 840μm×970μm. The in-band phase noise of the synthesizer is –107dBc/Hz at 10kHz offset, the in-band phase noise is more than 10dBc/Hz better than the one with the noise-folding problem. The integrated rms phase error is below 0.6°, the worst reference spur is below -74dBc when using the proposed PFD and the worst IRR is 45dB without any calibration and the locking time is less than 30μs. Keywords: Fractional-N Frequency Synthesizer, In-band Phase Noise, Reference Spurs, Circuit Nonlinearity, Linear Technique, Noise-folding Phenomenon, Linear PFD, Divider Chain

第一章绪论第一章绪论 1.1研究背景我们己经进入数字化的时代，人们对于数据传输的要求越来越高，加之现在数字设备正朝着便捷化、无线化发展，对于无线收发机的性能、集成化程度、功耗的要求也越来越高。各种用于语音和数据通信的协议不断的被开发出来，例如用于语音通信的GSM、CDMA、NCDMA、TD-SCDMA及LTE等，侧重于数据传输的Bluetooth、WIFl、WLAN及VIMAX等。对于数字电视(DTV)信号的接收而言，不同的国家和地区存在着不同的标准，如欧洲采用DVB-CT/S/H,北美地区采用ATSC,中国采用DVB-C/S和CMMB。并且随着人们对于高清电视(High Definition Television,HDTV)和视频点播 Video On Demand,.VOD)等功能的需求，下一代的数字电视标准也已经制定出来，在2009和2010年分别发表了下一代的数字电视标准DVB-T2/C2,而 DVB-S2也有希望在今年制定完成[1]。为了满足世界范围内所有的标准的要求，就要求射频接收机有足够宽的调谐范围：由于无线广播信道的复杂性、数字电视信号的高信噪比的要求，更为了满足下一代标准的要求，使得射频接收机对噪声的要求变得很高。而频率综合器作为射频接收机的本振(LO),将为其提供高频谱纯度的信号，频率综合器的噪声性能、杂散性能(Spu)将直接影响整个射频接收机的噪声性能。锁相环(PLL)型频率综合器由于具有结构简单，输出信号频谱纯度高以及输出频率易调谐等特点而被广泛采用，可分为整数分频锁相环和分数分频锁相环两种。由于整数分频锁相环的调谐精度由参考时钟决定，难以满足数字电视信号接收机(DTV-Tuner)对于带宽和锁定时间的要求。而分数分频锁相环打破了调谐精度和参考时钟的折衷，有了更高的设计自由度，设计高调谐精度、快速锁定的锁相环成为了可能。相对于整数分频锁相环，Σ△调制器的使用实现了分数分频的功能。在理想情况下，即环路中不存在失配(Mismatch),整个环路是线性的时候，∑△调制器由于自身的过采样(Over Sample)和噪声整形(Noise Shaping)的特性能够将自身产生的量化噪声搬移到高频频率处，同时由于锁相环系统自身的低通特性，高频的噪声会被环路滤掉，从而在带内(In-band)能够获得良好的相当于整数分频综合器的噪声特性。但是由于锁相环中的电荷泵(Charge Pump)中不可避免的存在失配，电路表现出一定的非线性，∑△调制器的过采样和噪声整形特性被破坏，高频带外量化噪声折叠回带内，低频的相位噪声被恶化，从而整个频率综合器的 1

第一章绪论 1 第一章绪论 1.1 研究背景我们已经进入数字化的时代，人们对于数据传输的要求越来越高，加之现在数字设备正朝着便捷化、无线化发展，对于无线收发机的性能、集成化程度、功耗的要求也越来越高。各种用于语音和数据通信的协议不断的被开发出来，例如用于语音通信的 GSM、CDMA、WCDMA、TD-SCDMA 及 LTE 等，侧重于数据传输的 Bluetooth、WIFI、WLAN 及 WIMAX 等。对于数字电视(DTV)信号的接收而言，不同的国家和地区存在着不同的标准，如欧洲采用 DVB-C/T/S/H，北美地区采用 ATSC，中国采用 DVB-C/S 和 CMMB。并且随着人们对于高清电视(High Definition Television, HDTV)和视频点播 (Video On Demand, VOD)等功能的需求，下一代的数字电视标准也已经制定出来，在 2009 和 2010 年分别发表了下一代的数字电视标准 DVB-T2/C2，而 DVB-S2 也有希望在今年制定完成[1]。为了满足世界范围内所有的标准的要求，就要求射频接收机有足够宽的调谐范围；由于无线广播信道的复杂性、数字电视信号的高信噪比的要求，更为了满足下一代标准的要求，使得射频接收机对噪声的要求变得很高。而频率综合器作为射频接收机的本振(LO)，将为其提供高频谱纯度的信号，频率综合器的噪声性能、杂散性能(Spur)将直接影响整个射频接收机的噪声性能。锁相环(PLL)型频率综合器由于具有结构简单，输出信号频谱纯度高以及输出频率易调谐等特点而被广泛采用，可分为整数分频锁相环和分数分频锁相环两种。由于整数分频锁相环的调谐精度由参考时钟决定，难以满足数字电视信号接收机(DTV-Tuner)对于带宽和锁定时间的要求。而分数分频锁相环打破了调谐精度和参考时钟的折衷，有了更高的设计自由度，设计高调谐精度、快速锁定的锁相环成为了可能。相对于整数分频锁相环，ΣΔ 调制器的使用实现了分数分频的功能。在理想情况下，即环路中不存在失配(Mismatch)，整个环路是线性的时候，ΣΔ 调制器由于自身的过采样(Over Sample)和噪声整形(Noise Shaping)的特性能够将自身产生的量化噪声搬移到高频频率处，同时由于锁相环系统自身的低通特性，高频的噪声会被环路滤掉，从而在带内(In-band)能够获得良好的相当于整数分频综合器的噪声特性。但是由于锁相环中的电荷泵(Charge Pump)中不可避免的存在失配，电路表现出一定的非线性，ΣΔ 调制器的过采样和噪声整形特性被破坏，高频带外量化噪声折叠回带内，低频的相位噪声被恶化，从而整个频率综合器的

分数分频频率综合器中噪声折叠问题的研究与电路设计输出相位噪声被恶化，达不到数字电视信号接收机对本振信号的噪声要求。因此解决电路非线性问题引起的噪声折叠(Noise-.Folding)现象具有十分重要的意义。另外，分数分频锁相环不可避免的产生了分数杂散(Fractional Spur)),这对输出信号的频谱程度也会产生一定的恶化。现在有许多很好的解决噪声折叠现象的技术，如增加额外的静态电流来使PFD工作在线性区，但是它在有效解决噪声折叠现象的同时恶化了系统参考杂散(Reference Spur)特性，加入采样环路滤波器(Sampled Loop Filter)的技术虽然避免恶化参考杂散特性，但是又带来了时钟馈通(Clock Feedthrough)和电荷注入(Charge Injection)的问题。因此，如何在解决了噪声折叠问题的同时，又获得良好的Spu「特性和避免带来其他问题也是本文研究的重点。 1.2论文主要贡献本论文主要针对∑△分数分频频率综合器中的电路非线性及杂散性能展开工作。消除了噪声折叠问题，提高了带内噪声性能，从而提高了输出噪声的性能，并且避免了参考杂散性能的恶化。在电路设计和版图设计的过程中都进行了充分的考虑，以获得较好的杂散性能。本文提出的技术和方法能够显著地降低锁相环带内噪声特性，能够获得低相位噪声，低积分均方根(s)相位误差、良好杂散 (Spu)性能的高性能分数分频频率综合器。本论文的主要贡献有： )分析了杂散的产生机制，分别针对参考杂散和分数杂散提出了优化方法，在电路和版图上进行了相应的设计。 2)根据∑△分数分频锁相环的噪声模型，分析了Σ△调制器的量化噪声到输出相位噪声的转换，确定了Σ△调制器的量化噪声对输出噪声的贡献。 3)分析了∑△分数分频锁相环的非线性特性，提出了在非线性存在的情况下相位噪声的模型。 4)提出了一种新型的线性鉴频鉴相器结构，消除了电路的非线性特性，降低了带内的噪声，提高了输出相位噪声特性。设计并测试了一款用于多标准数字电视标准的760MHz~1860MHz的分数分频频率综合器芯片，采用上述技术，获得了良好的测试性能。 1.3论文的研究内容和组织结构本论文主要分析了分数分频频率综合器中由于环路非线性引起的噪声折叠问题，通过对噪声折叠机制的理论分析得到能够指导电路设计的结果。介绍了提出的线性PFD以及分频器链的电路设计。论文个部分内容安排如下：第二章“锁相环性频率综合器概述”主要阐述了锁相环性频率综合器的原理，然后分析了频率综合器的几个重要参数，分析了这些参数的影响并且给出了 2

分数分频频率综合器中噪声折叠问题的研究与电路设计 2 输出相位噪声被恶化，达不到数字电视信号接收机对本振信号的噪声要求。因此解决电路非线性问题引起的噪声折叠(Noise-Folding)现象具有十分重要的意义。另外，分数分频锁相环不可避免的产生了分数杂散(Fractional Spur)，这对输出信号的频谱程度也会产生一定的恶化。现在有许多很好的解决噪声折叠现象的技术，如增加额外的静态电流来使 PFD 工作在线性区，但是它在有效解决噪声折叠现象的同时恶化了系统参考杂散(Reference Spur)特性，加入采样环路滤波器(Sampled Loop Filter)的技术虽然避免恶化参考杂散特性，但是又带来了时钟馈通(Clock Feedthrough)和电荷注入(Charge Injection)的问题。因此，如何在解决了噪声折叠问题的同时，又获得良好的 Spur 特性和避免带来其他问题也是本文研究的重点。 1.2 论文主要贡献本论文主要针对ΣΔ分数分频频率综合器中的电路非线性及杂散性能展开工作。消除了噪声折叠问题，提高了带内噪声性能，从而提高了输出噪声的性能，并且避免了参考杂散性能的恶化。在电路设计和版图设计的过程中都进行了充分的考虑，以获得较好的杂散性能。本文提出的技术和方法能够显著地降低锁相环带内噪声特性，能够获得低相位噪声，低积分均方根(rms)相位误差、良好杂散 (Spur)性能的高性能分数分频频率综合器。本论文的主要贡献有： 1) 分析了杂散的产生机制，分别针对参考杂散和分数杂散提出了优化方法，在电路和版图上进行了相应的设计。 2) 根据 ΣΔ 分数分频锁相环的噪声模型，分析了 ΣΔ 调制器的量化噪声到输出相位噪声的转换，确定了 ΣΔ 调制器的量化噪声对输出噪声的贡献。 3) 分析了 ΣΔ 分数分频锁相环的非线性特性，提出了在非线性存在的情况下相位噪声的模型。 4) 提出了一种新型的线性鉴频鉴相器结构，消除了电路的非线性特性，降低了带内的噪声，提高了输出相位噪声特性。设计并测试了一款用于多标准数字电视标准的 760 MHz~1860 MHz 的分数分频频率综合器芯片，采用上述技术，获得了良好的测试性能。 1.3 论文的研究内容和组织结构本论文主要分析了分数分频频率综合器中由于环路非线性引起的噪声折叠问题，通过对噪声折叠机制的理论分析得到能够指导电路设计的结果。介绍了提出的线性 PFD 以及分频器链的电路设计。论文个部分内容安排如下：第二章 “锁相环性频率综合器概述”主要阐述了锁相环性频率综合器的原理，然后分析了频率综合器的几个重要参数，分析了这些参数的影响并且给出了